Digital and Mixed Signal RF Digital Signal Processing for RF Informational

What is the CORDIC algorithm and how is it used in digital RF signal processing?

Q: How many CORDIC iterations do I need?

The number of iterations equals the desired bit precision: for 12-bit output: 12 iterations (11-bit accuracy). For 16-bit output: 16 iterations (15-bit accuracy, 0.003° phase error). For 24-bit output: 24 iterations (23-bit accuracy). Each iteration adds one pipeline stage (one clock cycle of latency). For a 250 MHz FPGA clock with 16 iterations: latency = 16 × 4 ns = 64 ns. Throughput: one result per clock cycle (4 ns) after the pipeline fills.

Q: Can CORDIC compute other functions?

Yes. Beyond sin/cos and arctan: (1) Hyperbolic CORDIC: uses hyperbolic rotations to compute sinh, cosh, and tanh. Used for: exponential functions and logarithms. (2) Linear CORDIC: computes multiplication and division using only shifts and adds. (3) Sqrt(x): by combining rotation and vectoring modes. (4) Log2(x) and exp2(x): using logarithmic CORDIC. These extended CORDIC modes are used in DSP applications where multipliers are scarce (ASIC design, low-power FPGA).

Q: Is CORDIC used in modern 5G systems?

Yes. CORDIC is used extensively in 5G digital baseband and beamforming: (1) Digital beamforming in gNB: CORDIC rotates each antenna element signal by the beamforming phase. For 64T64R massive MIMO: 64 CORDIC instances per subcarrier × hundreds of subcarriers. (2) CFO correction (carrier frequency offset): CORDIC rotates the received samples to correct for frequency offset between TX and RX. (3) OFDM tone mapping: CORDIC maps the frequency-domain symbols to time-domain samples (part of the IFFT/FFT processing chain). (4) Digital predistortion: some DPD architectures use CORDIC for polar decomposition (converting I/Q to amplitude/phase for the predistortion LUT).

CORDIC (COordinate Rotation DIgital Computer) is an iterative algorithm that computes trigonometric functions, magnitude, phase, and complex rotations using only shift and add operations (no multipliers needed). This makes it extremely efficient for FPGA and hardware implementation in digital RF systems. The algorithm works by rotating a vector through a sequence of predetermined angles: (1) Rotation mode: given an angle theta, CORDIC rotates the input vector [x, y] by theta. At each iteration i: x_new = x - d_i × y × 2^(-i), y_new = y + d_i × x × 2^(-i), z_new = z - d_i × arctan(2^(-i)). Where d_i = +1 or -1 (chosen to drive z toward zero). After N iterations: [x_new, y_new] = [x×cos(theta) - y×sin(theta), x×sin(theta) + y×cos(theta)] (the rotated vector). This computes sin(theta) and cos(theta) simultaneously. Used in: digital down-conversion (NCO: numerically controlled oscillator), IQ modulation/demodulation, and phase rotation for beamforming. (2) Vectoring mode: given a vector [x, y], CORDIC rotates it to the x-axis, outputting the magnitude (sqrt(x² + y²)) and the phase (arctan(y/x)). At each iteration: d_i is chosen to drive y toward zero. After N iterations: x_final = K × sqrt(x² + y²) (magnitude), z_final = arctan(y/x) (phase). Where K = 1.6468 (the CORDIC gain, a constant). Used in: FM demodulation (phase extraction), amplitude and phase measurement, and polar modulation. (3) FPGA implementation: each iteration requires only two shifts and two additions (no multipliers). An N-bit CORDIC takes N iterations (N pipeline stages). Latency: N clock cycles. Throughput: one result per clock cycle (pipelined). Resource usage: approximately 3N adders + control logic (very efficient; a 16-bit CORDIC uses approximately 48 adders). Accuracy: N-bit CORDIC provides approximately N-1 bits of accuracy. For 16-bit: accuracy ≈ 0.003° in phase, ≈ 15-bit in magnitude.

Category: Digital and Mixed Signal RF

Updated: April 2026

Product Tie-In: FPGAs, SDR Platforms, DSP Modules

CORDIC in Digital RF

CORDIC is one of the most widely used algorithms in digital RF hardware, appearing in virtually every SDR, digital beamformer, and radar signal processor.

Parameter	Pipeline ADC	SAR ADC	Sigma-Delta ADC
Sample Rate	100 MS/s - 10 GS/s	1-100 MS/s	10 kS/s - 50 MS/s
Resolution	8-14 bits	10-20 bits	16-24 bits
Latency	Several clock cycles	1 conversion cycle	Many cycles (decimation)
Power	High	Low-moderate	Low
Typical RF Use	Direct sampling, DPD	Control, monitoring	Audio, baseband

Sampling and Quantization

(1) NCO (Numerically Controlled Oscillator): generates sin and cos waveforms at a programmable frequency. A phase accumulator adds a frequency word each clock cycle. CORDIC converts the accumulated phase to sin/cos samples. The NCO replaces the analog LO in a digital receiver (digital down-conversion). Performance: SFDR > 90 dBc (for a 32-bit phase accumulator with a 16-bit CORDIC). (2) Digital down-conversion (DDC): the received IF signal is multiplied by the NCO output (complex multiplication). This shifts the signal from IF to baseband. CORDIC performs this rotation directly (rotate the input sample by the NCO phase). No explicit multipliers needed. (3) Digital beamforming: each antenna element signal is phase-shifted (rotated) by a different angle to steer the beam. CORDIC rotates each complex sample by the beamforming weight angle. For a 256-element array: 256 CORDIC instances run in parallel (one per element). This is highly efficient in FPGA fabric. (4) FM demodulation: FM is modulated by the instantaneous frequency, which is the derivative of the phase. CORDIC vectoring mode extracts the phase of the input signal. Differentiating the phase yields the FM modulated signal. CORDIC-based FM demodulation is exact (no approximation) and very efficient. (5) Polar modulation/demodulation: some transmitter architectures modulate the amplitude and phase separately (polar modulation). CORDIC converts between Cartesian (I, Q) and polar (amplitude, phase) representations efficiently.

Performance verification: confirm specifications against the application requirements before finalizing the design
Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture

Dynamic Range Considerations

(1) A complex multiplication (I×cos - Q×sin, I×sin + Q×cos) requires 4 multiplications and 2 additions. In FPGA: 4 DSP blocks + 2 adders per operation. (2) CORDIC performs the same rotation using approximately 32-48 adders (for 16-bit precision) and 0 multipliers. In FPGA: CORDIC uses logic fabric (LUTs and registers), leaving the DSP blocks free for other computations (FIR filters, FFTs). (3) For a digital beamformer with 256 elements: multiplier approach: 256 × 4 = 1024 DSP blocks. CORDIC approach: 0 DSP blocks (all in logic fabric). The CORDIC approach is preferred when DSP block resources are limited (common in mid-range FPGAs). (4) Accuracy: multiplier approach: exact (limited only by the word length). CORDIC approach: approximately N-1 bits accurate for N iterations. For 16-bit: 15-bit accuracy (< 0.01% error). This is adequate for virtually all RF applications.

Common Questions

Frequently Asked Questions

How many CORDIC iterations do I need?

The number of iterations equals the desired bit precision: for 12-bit output: 12 iterations (11-bit accuracy). For 16-bit output: 16 iterations (15-bit accuracy, 0.003° phase error). For 24-bit output: 24 iterations (23-bit accuracy). Each iteration adds one pipeline stage (one clock cycle of latency). For a 250 MHz FPGA clock with 16 iterations: latency = 16 × 4 ns = 64 ns. Throughput: one result per clock cycle (4 ns) after the pipeline fills.

Can CORDIC compute other functions?

Yes. Beyond sin/cos and arctan: (1) Hyperbolic CORDIC: uses hyperbolic rotations to compute sinh, cosh, and tanh. Used for: exponential functions and logarithms. (2) Linear CORDIC: computes multiplication and division using only shifts and adds. (3) Sqrt(x): by combining rotation and vectoring modes. (4) Log2(x) and exp2(x): using logarithmic CORDIC. These extended CORDIC modes are used in DSP applications where multipliers are scarce (ASIC design, low-power FPGA).

Is CORDIC used in modern 5G systems?

Yes. CORDIC is used extensively in 5G digital baseband and beamforming: (1) Digital beamforming in gNB: CORDIC rotates each antenna element signal by the beamforming phase. For 64T64R massive MIMO: 64 CORDIC instances per subcarrier × hundreds of subcarriers. (2) CFO correction (carrier frequency offset): CORDIC rotates the received samples to correct for frequency offset between TX and RX. (3) OFDM tone mapping: CORDIC maps the frequency-domain symbols to time-domain samples (part of the IFFT/FFT processing chain). (4) Digital predistortion: some DPD architectures use CORDIC for polar decomposition (converting I/Q to amplitude/phase for the predistortion LUT).

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