Amplifier Selection and Design LNA Selection and Design Informational

What is the maximum available gain of a transistor and how do I calculate it from S-parameters?

The maximum available gain (MAG) is the highest power gain achievable from a transistor when both input and output are simultaneously conjugate-matched. MAG = |S21/S12| × (K - √(K²-1)), valid only when K > 1 (unconditionally stable). When K < 1, MAG is undefined, and the maximum stable gain (MSG) = |S21/S12| applies as an upper bound. MAG decreases at approximately 6 dB/octave with increasing frequency. At the frequency where K = 1, MAG = MSG, and this is the maximum frequency for stable conjugate-matched operation.
Category: Amplifier Selection and Design
Updated: April 2026
Product Tie-In: LNAs, Transistors, Bias Tees

MAG and MSG Calculation

The S-parameters of a transistor completely describe its small-signal RF behavior. From these, the maximum gain under various matching conditions can be calculated. The three gain metrics are: (1) MAG (maximum available gain): the gain under simultaneous conjugate match, valid for K > 1; (2) MSG (maximum stable gain): the gain when K = 1, representing the theoretical limit before instability; (3) transducer gain GT: the actual gain for specific source and load impedances, always less than MAG.

ParameterLNADriverPower Amplifier
Noise Figure0.3-2.0 dB3-8 dB5-15 dB (not specified)
Gain10-25 dB10-20 dB8-15 dB
P1dB-10 to +10 dBm+15 to +25 dBm+30 to +50 dBm
OIP3+5 to +25 dBm+25 to +40 dBm+40 to +55 dBm
DC Power10-100 mW0.5-5 W5-500 W
  • Performance verification: confirm specifications against the application requirements before finalizing the design
  • Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
  • Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
Common Questions

Frequently Asked Questions

Why is MAG higher than the gain I measure?

MAG assumes perfect simultaneous conjugate matching, which is difficult to achieve in practice. Any mismatch at input or output reduces the gain below MAG. Also, stabilization resistors and practical matching network losses reduce available gain.

What is the unilateral figure of merit?

It quantifies how close the transistor is to unilateral (S12 = 0). U = |S12||S21||S11||S22| / ((1-|S11|²)(1-|S22|²)). If U < 0.1, the unilateral approximation is valid and unilateral gain is within 1 dB of the true MAG. This simplifies matching design by allowing input and output to be matched independently.

How many stages do I need?

Divide the required gain by the MAG per stage (with practical derating of 2-3 dB for matching losses and stability resistors). For example, 40 dB gain with a transistor providing 15 dB MAG at the operating frequency requires 3 stages (3 × 15 = 45 dB MAG, nets ~40 dB with losses).

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