What is the effect of solder void percentage on the thermal resistance of a power device attachment?

The effect of solder void percentage on the thermal resistance of a power device attachment is that voids (gas-filled pockets) in the solder layer between the device die and the package or substrate reduce the effective thermal conductivity of the solder joint, increasing the thermal resistance and raising the device's junction temperature. Solder voids are caused by: outgassing from the solder flux during reflow, trapped gas from the soldering atmosphere, and poor wetting of the die or substrate surface. The effect depends on: the total void area percentage (the fraction of the solder joint area occupied by voids; IPC-7095 recommends < 25% total void area for power devices, and < 10% for high-reliability applications), the void location (voids directly under the active die area are worse than voids at the periphery because they block heat flow from the hottest region), and the void size distribution (a few large voids are worse than many small voids because large voids create larger thermal bottlenecks; a single void covering > 10% of the die area can increase thermal resistance by > 20%). The thermal resistance increase is: R_solder_with_voids = R_solder_ideal / (1 - void_fraction) for uniformly distributed small voids (a simple model). For 25% voids: R increases by 33%. For 50% voids: R increases by 100% (doubles). In reality: the non-uniform distribution and thermal spreading effects make the actual impact somewhat less severe than this worst-case formula for small voids, but large concentrated voids can be even worse than the formula predicts.