What is the relationship between channel temperature and gate lag in a GaN HEMT?

The relationship between channel temperature and gate lag in a GaN HEMT involves the interaction between thermal effects and charge trapping mechanisms that cause the drain current to respond slowly to changes in gate voltage. Gate lag is the phenomenon where the drain current does not reach its expected value immediately after the gate voltage changes from pinch-off to the on-state; instead, the current starts at a lower value and gradually increases to its steady-state level over a time scale of microseconds to milliseconds. The relationship to channel temperature is: at higher channel temperatures, the gate lag effect generally worsens because elevated temperature increases: the density of thermally activated trap states at the AlGaN/GaN interface and in the GaN buffer that capture and slowly release electrons (traps at the surface capture electrons during the off-state, and these trapped charges act as a parasitic negative gate bias that reduces the drain current when the device turns on; the release of these trapped charges is thermally activated, with emission rates that increase with temperature, but the equilibrium trap occupancy also increases at higher temperatures), the thermal activation of deep-level traps in the GaN buffer layer (iron, carbon, or other dopants used to make the buffer semi-insulating create deep trap levels that capture electrons from the 2DEG channel; higher temperature increases the capture rate and decreases the emission rate for some trap species), and the degradation of the 2DEG density at elevated temperatures (the spontaneous and piezoelectric polarization charges that form the 2DEG are temperature-dependent, reducing the available channel charge at high temperatures). Gate lag is quantified as the gate lag ratio: GLR = I_ds_pulsed(t) / I_ds_DC, where a GLR of 1.0 indicates no gate lag and values less than 1.0 indicate current reduction due to trapping.