What is the effect of ground via placement on the performance of a shunt matching component?
Ground Via Impact on Shunt Components
Ground via placement is the single most common cause of matching network detuning on PCB implementations. Many designers underestimate the via inductance and are surprised when their matching network performs differently from the simulation that assumed an ideal ground.
| Parameter | L-Network | Pi/T-Network | Transmission Line |
|---|---|---|---|
| Bandwidth | Narrow (<10%) | Moderate (10-30%) | Broad (>30%) |
| Components | 2 (L, C) | 3 (L, C, C or C, L, C) | Stubs, lines |
| Q Control | Fixed by impedance ratio | Adjustable | Set by line length |
| Frequency Range | DC-6 GHz | DC-6 GHz | 1-100+ GHz |
| Design Complexity | Low | Medium | Medium-high |
- Performance verification: confirm specifications against the application requirements before finalizing the design
- Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
- Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
- Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture
Frequently Asked Questions
How do I include via inductance in my simulation?
For circuit simulation (ADS, AWR): add a series inductor (0.3-0.5 nH per via) between the shunt component and the ideal ground. For EM simulation (HFSS, CST, Sonnet): model the actual via geometry (hole diameter, pad diameter, antipad diameter, substrate thickness) in the 3D model. The EM simulator will automatically capture the via inductance and its interaction with the surrounding ground plane. Best practice: always use EM simulation for matching networks above 3 GHz to capture all via and pad parasitic effects.
What about via pad capacitance?
The via pad (the copper annular ring around the via hole) creates parasitic capacitance to the surrounding ground plane on other layers. The via antipad (the clearance hole in the ground plane) reduces this capacitance. For a via with 0.6 mm pad diameter and 1.0 mm antipad through a 0.8 mm substrate: the pad capacitance is approximately 0.05-0.1 pF. This capacitance resonates with the via inductance at: f_res = 1/(2π×sqrt(LC)) ≈ 10-20 GHz for typical dimensions. Above this resonance: the via behaves more like a capacitor than an inductor, which may actually be beneficial for some applications.
Is there a rule of thumb for maximum via distance?
Rule of thumb: the ground via should be within lambda/30 of the component pad (where lambda is the wavelength in the substrate). At 5 GHz on Rogers 4350B (effective lambda approximately 40 mm): the via should be within 1.3 mm of the pad. At 10 GHz: within 0.65 mm. At 20 GHz: within 0.33 mm. Closer is always better. The practical minimum distance depends on the PCB design rules (minimum trace spacing, via-to-pad clearance). Via-in-pad (zero distance) is the ideal solution.