Millimeter Wave Specific Challenges mmWave Design Challenges Informational

What are the packaging challenges for millimeter wave integrated circuits above 60 GHz?

Q: Can I use a standard QFN package above 60 GHz?

No. Standard QFN packages (lead frame + wire bond) have severe limitations above 20-30 GHz: (1) Wire bond inductance makes the signal transition unusable above 30 GHz. (2) The QFN cavity resonates at 30-50 GHz (depending on cavity size). (3) The lead frame connection (bond pad → lead frame → solder joint) adds 0.5-1.5 dB loss at 40 GHz. Above 60 GHz: only WLP, eWLB, AiP, or CoB approaches are viable. Custom packages with flip-chip on low-loss substrates (alumina, glass, LTCC) can work if carefully designed with 3D EM simulation. Some companies offer "mmWave QFN" packages with special features: air cavity (to reduce substrate mode excitation), flip-chip die attach (no wire bonds), and controlled-impedance leads. These work to 40-50 GHz but are still marginal above 60 GHz.

Q: What is the difference between fan-in and fan-out WLP?

Fan-in WLP (FIWLP): the RDL and solder balls are placed within the die footprint. The package is the same size as the die. Suitable for die with relatively few I/O pads (< 100 bumps). Used for: small mmWave ICs (PA, LNA, single-function MMICs). Fan-out WLP (FOWLP, eWLB): the die is embedded in a mold compound, and the RDL extends beyond the die edge. The package is larger than the die. The fan-out area provides space for: additional solder balls (more I/O), antenna elements, embedded passives (capacitors, inductors in the RDL), and thermal vias to the bottom of the package. FOWLP is the approach used by Infineon for 77 GHz radar (the antenna is in the fan-out area) and is under evaluation for 5G mmWave AiP.

Q: How do I validate the package design?

Validation must include both EM simulation and physical measurement: (1) EM simulation: model the complete package (die, flip-chip bumps, substrate, solder balls, and PCB landing pads) in a 3D EM solver. Simulate S-parameters from the die port to the board port. Target: insertion loss 15 dB across the operating band. (2) Physical measurements: fabricate test packages with known die (or calibration structures in place of a die). Measure the package S-parameters using on-wafer probes or specialized package test fixtures. Compare with simulation. Iterate the design if needed. (3) Reliability testing: thermal cycling (-40 to +125°C, 1000 cycles for automotive, 500 for commercial). Humidity testing (85°C/85% RH, 1000 hours). Drop test for consumer devices. The package must maintain < 1 dB insertion loss after reliability testing.

Packaging mmWave ICs above 60 GHz introduces extreme challenges because the wavelength is so short (5 mm at 60 GHz, 2.5 mm at 120 GHz) that every physical feature in the package becomes a significant electromagnetic structure: (1) Package interconnect loss: standard wire bonds become unusable (L = 0.5 nH → Z = 188 ohms at 60 GHz). Flip-chip bumps are the minimum requirement: L = 0.03-0.1 nH → Z = 11-38 ohms at 60 GHz (manageable with compensation). Even flip-chip adds measurable loss: 0.2-0.5 dB per transition at 60 GHz. (2) Package substrate loss: the package substrate must carry the RF signal from the die to the external port (antenna, connector, or board pad). At 60 GHz: the substrate loss is significant: HTCC alumina: 0.3-0.5 dB/cm (usable but adds to the total budget). LTCC: 0.2-0.4 dB/cm (good). Organic: 0.3-0.8 dB/cm (depends on laminate quality). For a 5 mm interconnect on the package substrate: 0.1-0.4 dB loss (non-trivial when the total system loss budget may be only 3-5 dB). (3) Package resonances: the package cavity can resonate at mmWave frequencies. For a typical QFN cavity (5 × 5 × 0.5 mm): first resonance at approximately 30 GHz. Above 30 GHz: multiple resonant modes exist within the package cavity. At resonance: the package mismatch increases dramatically (potential oscillation, gain peaking, or severe loss). Suppression: fill the cavity with low-loss epoxy or globtop (reduces the Q of the resonance). Add absorber material inside the cavity. Use a packageless design (flip-chip directly on the board or AiP substrate). (4) Mode coupling: the package can support waveguide modes (surface waves, substrate modes) that steal energy from the desired signal path. At 60+ GHz: substrate modes are easily excited in thick substrates (h > lambda/(4×sqrt(epsilon_r))). Mode coupling creates ripple in the frequency response and reduces the effective bandwidth.

Category: Millimeter Wave Specific Challenges

Updated: April 2026

Product Tie-In: mmWave Components, Substrates, Packaging

mmWave IC Packaging

Above 60 GHz, the traditional approach of designing the IC first and then packaging it separately becomes impractical. The package must be co-designed with the IC and (often) the antenna.

Technical Considerations

(1) Wafer-level packaging (WLP): the die is packaged at the wafer level using redistribution layers (RDL) to fan out the die pads to a standard ball grid array. No package substrate, no wire bonds, no cavity. The die is mounted directly on the PCB. Advantages: minimum interconnect length (the RDL is < 20 um thick), no package parasitics, smallest form factor, lowest cost at high volume. Challenges: the bare die is exposed (reliability concerns: moisture, mechanical shock). An overmold or globtop is applied for protection, which affects the RF performance. (2) Embedded wafer-level ball grid array (eWLB): the die is embedded in a molding compound, and the RDL is formed over the mold surface (fan-out). This allows the RDL to extend beyond the die edge, providing space for antenna elements and passive components. Used in: Infineon 77 GHz radar SoC (the antenna is on the eWLB RDL). The antenna is within 50 um of the die, eliminating the package-to-board-to-antenna transition. (3) Antenna-in-Package (AiP): the package substrate includes antenna elements (patches, slots, dipoles) as part of the package. The die connects to the antenna through the package substrate (LTCC, organic, or glass). No external antenna or antenna transition is needed. The AiP approach eliminates the most lossy transition (package-to-board-to-antenna) and is standard for 5G UE mmWave modules and some automotive radar. Qualcomm QTM525: organic AiP with integrated 4-element phased array. TI AWR1843: eWLB AiP with on-package patch antenna array. (4) Chip-on-board (CoB): the bare die is directly attached (wire-bonded or flip-chip) to the final PCB substrate. No package at all. The PCB substrate provides the interconnects, passives, and antenna. Advantages: lowest loss (no package layers). Used in: high-performance military and research mmWave systems. Challenges: the bare die requires clean room handling and is vulnerable to contamination and mechanical damage.

Performance verification: confirm specifications against the application requirements before finalizing the design
Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture

Performance Analysis

At 60+ GHz: the die size is very small (often 1 × 1 mm or less for a single MMIC). The power density is extremely high. The package must provide: thermal path from the die to the heatsink (through the substrate or through backside thermal vias). CTE matching between the die and substrate (to prevent solder joint fatigue). Mechanical protection (the thin die is fragile). Hermeticity (for long-life applications: military, space). These requirements often conflict: the best thermal solution (thin substrate, large backside pad) may not provide adequate mechanical protection. The best hermetic seal (metal lid, seam-welded) creates a cavity that resonates. Co-optimization of thermal, mechanical, and RF performance is essential.

Common Questions

Frequently Asked Questions

Can I use a standard QFN package above 60 GHz?

No. Standard QFN packages (lead frame + wire bond) have severe limitations above 20-30 GHz: (1) Wire bond inductance makes the signal transition unusable above 30 GHz. (2) The QFN cavity resonates at 30-50 GHz (depending on cavity size). (3) The lead frame connection (bond pad → lead frame → solder joint) adds 0.5-1.5 dB loss at 40 GHz. Above 60 GHz: only WLP, eWLB, AiP, or CoB approaches are viable. Custom packages with flip-chip on low-loss substrates (alumina, glass, LTCC) can work if carefully designed with 3D EM simulation. Some companies offer "mmWave QFN" packages with special features: air cavity (to reduce substrate mode excitation), flip-chip die attach (no wire bonds), and controlled-impedance leads. These work to 40-50 GHz but are still marginal above 60 GHz.

What is the difference between fan-in and fan-out WLP?

Fan-in WLP (FIWLP): the RDL and solder balls are placed within the die footprint. The package is the same size as the die. Suitable for die with relatively few I/O pads (< 100 bumps). Used for: small mmWave ICs (PA, LNA, single-function MMICs). Fan-out WLP (FOWLP, eWLB): the die is embedded in a mold compound, and the RDL extends beyond the die edge. The package is larger than the die. The fan-out area provides space for: additional solder balls (more I/O), antenna elements, embedded passives (capacitors, inductors in the RDL), and thermal vias to the bottom of the package. FOWLP is the approach used by Infineon for 77 GHz radar (the antenna is in the fan-out area) and is under evaluation for 5G mmWave AiP.

How do I validate the package design?

Validation must include both EM simulation and physical measurement: (1) EM simulation: model the complete package (die, flip-chip bumps, substrate, solder balls, and PCB landing pads) in a 3D EM solver. Simulate S-parameters from the die port to the board port. Target: insertion loss < 1 dB and return loss > 15 dB across the operating band. (2) Physical measurements: fabricate test packages with known die (or calibration structures in place of a die). Measure the package S-parameters using on-wafer probes or specialized package test fixtures. Compare with simulation. Iterate the design if needed. (3) Reliability testing: thermal cycling (-40 to +125°C, 1000 cycles for automotive, 500 for commercial). Humidity testing (85°C/85% RH, 1000 hours). Drop test for consumer devices. The package must maintain < 1 dB insertion loss after reliability testing.

Keep Reading