How do I select the bias point of an LNA to minimize noise figure?
Noise Bias Optimization
The noise figure of a transistor depends on the bias point because the noise sources within the device (thermal noise in channel resistance, shot noise at the gate, and 1/f noise) all vary with current. At very low drain current, the transconductance is low and the gain is insufficient to suppress subsequent stage noise, so the system noise figure is high. At high drain current, the channel noise current increases faster than the transconductance, so NFmin increases.
| Parameter | LNA | Driver | Power Amplifier |
|---|---|---|---|
| Noise Figure | 0.3-2.0 dB | 3-8 dB | 5-15 dB (not specified) |
| Gain | 10-25 dB | 10-20 dB | 8-15 dB |
| P1dB | -10 to +10 dBm | +15 to +25 dBm | +30 to +50 dBm |
| OIP3 | +5 to +25 dBm | +25 to +40 dBm | +40 to +55 dBm |
| DC Power | 10-100 mW | 0.5-5 W | 5-500 W |
Bias and Operating Point
The optimum bias for noise is device-dependent. For depletion-mode GaAs pHEMTs: Vds = 1.5-3V, Ids = 10-20% of Idss. Lower Vds reduces power dissipation and thermal noise. Higher Vds provides more dynamic range (higher IIP3) at the cost of slightly higher noise. Many data sheets specify noise performance at multiple bias points to guide the designer.
- Performance verification: confirm specifications against the application requirements before finalizing the design
- Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
- Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
- Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture
- Margin allocation: include sufficient design margin to account for manufacturing tolerances and aging effects
Stability Considerations
For power-conscious designs (battery-operated, space), the LNA can be biased at a lower current with 0.3-1 dB noise figure penalty. This trades sensitivity for power consumption. Some LNA MMICs include a programmable bias to allow the system to dynamically adjust between low-power (higher NF) and full-performance (lower NF) modes.
Frequently Asked Questions
Does Vds affect noise figure?
Yes, slightly. Lower Vds reduces the drain-source noise by reducing the electric field in the channel. A GaAs pHEMT at Vds=1V may have 0.1-0.2 dB lower NF than at Vds=3V. However, too low a Vds reduces the gain and compression point. The optimum Vds is usually 1.5-2V for GaAs pHEMTs.
What about temperature?
Noise figure increases with temperature because all thermal noise sources scale with absolute temperature: NF(T) ≈ NFmin(T0) + (T-T0)/T0. At -40°C: NF improves by ~0.3 dB. At +85°C: NF degrades by ~0.5 dB compared to 25°C. Cryogenic cooling to 15K dramatically reduces NF to 0.05-0.2 dB for radio astronomy and deep-space applications.
How critical is the bias accuracy?
NFmin varies slowly near the optimum bias point. A ±20% variation in drain current typically changes NF by less than 0.2 dB. The bias circuit does not need extreme precision, but it must be stable over temperature. Use a stable current source rather than a voltage source for best NF stability.