How do I perform a load pull measurement on a power transistor?
Load Pull Measurement Technique
Load pull is the fundamental measurement technique for power amplifier design because the optimal transistor performance depends on the load impedance, which cannot be predicted accurately from device models alone (especially at high power and high frequencies).
| Parameter | SOLT Cal | TRL Cal | eCal |
|---|---|---|---|
| Accuracy | Good | Excellent | Good-very good |
| Standards Needed | 4 (S,O,L,T) | 3 (T,R,L) | 1 (module) |
| Bandwidth | Broadband | Band-limited | Broadband |
| Setup Time | 5-10 min | 10-20 min | 1-2 min |
| Best For | Coaxial, general | On-wafer, waveguide | Production, speed |
Calibration Procedure
The output of a load pull measurement is a set of constant-performance contours on the Smith chart: (1) Power contours: concentric ovals centered on Z_opt_power (the impedance for maximum output power). The contours are spaced at 1 dB intervals. The contour shape reveals how sensitive the device is to impedance mismatch. Narrow, elongated contours: the device is very sensitive to reactive impedance changes. Broad, circular contours: the device is tolerant of impedance variation (easier to design a broadband matching network). (2) Efficiency contours: centered on Z_opt_PAE, which is typically offset from Z_opt_power (higher impedance). For a class B amplifier: Z_opt_PAE ≈ 2 × V_dd^2 / P_out (the optimal load resistance for maximum swing). Z_opt_power is lower (more current flows but with less voltage swing). (3) Linearity contours (ACPR, EVM): the impedance for best linearity is often at a lower power level than Z_opt_power. There may be "sweet spots" where nonlinear products partially cancel. (4) Gain contours: centered on the conjugate match impedance (Z_opt_gain = S22*). Generally more circular than power contours.
Error Sources
For high-efficiency PA modes (class F, class J, continuous class modes): the impedance at the fundamental frequency AND the harmonic frequencies (2f0, 3f0) must be controlled. Harmonic load pull: (1) Adds harmonic tuners (mechanical or active) at 2f0 and 3f0 on the output. (2) At the fundamental: present the optimal Z for power or efficiency. (3) At 2f0: for class F: present a short circuit (Z_2f0 → 0, reflecting the second harmonic back into the device). For inverse class F: present an open circuit. (4) At 3f0: present an open circuit (class F) or short (inverse class F). (5) The harmonic load pull maps the PAE as a function of both fundamental and harmonic impedances. The optimal harmonic terminations can improve PAE by 10-20 percentage points compared to the fundamental-only optimum. Example: a GaN HEMT at 3.5 GHz with fundamental load pull only: PAE_max = 55%. With optimized 2nd and 3rd harmonic terminations: PAE_max = 75%.
- Performance verification: confirm specifications against the application requirements before finalizing the design
- Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
- Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
- Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture
Fixture Considerations
Source pull varies the source impedance (Z_S) presented to the transistor input. Objectives: (1) Find the source impedance for maximum gain (conjugate match of S11). (2) Find the source impedance for minimum noise figure (Z_opt_noise, from noise parameters). (3) Find the source impedance for best input match (minimum S11 of the amplifier). In noise figure-optimized LNA design: source pull identifies the optimal Z_S for minimum NF, which is typically different from the conjugate match. The resulting "noise circles" and "gain circles" on the Smith chart are used to find the best compromise between NF and gain.
Frequently Asked Questions
How many impedance points do I need for a load pull?
The number of points depends on the required contour resolution: for a coarse survey (identifying the optimal impedance region): 50-100 points in a grid covering the Smith chart. Measurement time: 5-15 minutes. For fine optimization (1 dB contour spacing, accurate contour shape): 200-400 points concentrated around the optimal impedance region. Measurement time: 30-60 minutes. For harmonic load pull (varying fundamental + 2f + 3f): the number of combinations increases dramatically: 100 fundamental × 50 at 2f × 20 at 3f = 100,000 combinations. Automated tuner systems with pre-calibrated lookup tables can measure this in 2-8 hours.
What is active load pull and when do I need it?
Active load pull uses a signal injection amplifier to synthesize the load impedance electronically (instead of a passive tuner). The injected signal adds to the reflected wave from the DUT, creating any desired reflection coefficient. Advantages: can present |Gamma| > 1 (negative resistance, for oscillator testing). Full Smith chart coverage (no blind spots near the center). Much faster impedance switching (microseconds vs seconds for mechanical tuners). Higher impedance accuracy (no mechanical hysteresis or repeatability issues). When to use: high-power devices where the optimal impedance is near the edge of the Smith chart (|Gamma| > 0.9). High-frequency devices (above 30 GHz) where mechanical tuner losses reduce the achievable |Gamma|. Rapid automated testing in production. Initial development with many impedance points needed.
How do I use load pull data to design a matching network?
The load pull contours tell you the target impedance for the output matching network: (1) Select the design objective (maximum power, maximum PAE, or best linearity). (2) Identify the corresponding optimal impedance from the load pull data: Z_opt = R + jX (at the measurement frequency). (3) Design a matching network that transforms 50 ohms to Z_opt at the design frequency. Common topologies: L-network (simplest, narrowband), pi-network (more flexibility), stub matching, or distributed (microstrip) matching for MMIC/PCB designs. (4) For broadband matching: examine how the optimal impedance varies with frequency. Design the matching network to track the Z_opt trajectory across the band. (5) Validate: simulate the matching network connected to the transistor large-signal model, and verify that the simulated performance matches the load pull predictions. Then build and test the prototype.