Millimeter Wave Specific Challenges mmWave Design Challenges Informational

How do I design a millimeter wave system on chip versus a system in package?

Q: How do I estimate the cost of SoC vs SiP?

SoC cost model: NRE (non-recurring engineering): $5M-50M (mask set: $2M-10M for advanced CMOS; design: $3M-40M). Die cost: die_area × wafer_cost / (die_per_wafer × yield). For a 10 mm² die in 28 nm CMOS: die cost ≈ $2-5. Package: $0.50-2.00 (standard QFN or WLP). Total unit cost: $3-7 at high volume. SiP cost model: each die is purchased or fabricated separately (lower NRE per die, $0.5M-5M total). Assembly cost: $1-5 (die attach, wire bond/flip-chip, substrate fabrication). Package/substrate: $2-10 (LTCC or organic with embedded antenna). Total unit cost: $10-30 at moderate volume. The crossover: SoC becomes cheaper than SiP at volumes above approximately 500K-2M units (where the high NRE is amortized).

At millimeter-wave frequencies, system integration takes two primary forms: System-on-Chip (SoC) and System-in-Package (SiP). Each offers different tradeoffs in performance, cost, and flexibility. (1) System-on-Chip (SoC): all functions (PA, LNA, mixer, synthesizer, ADC/DAC, digital baseband, and potentially the antenna) are integrated on a single semiconductor die. Technology: SiGe BiCMOS or advanced CMOS (65 nm, 28 nm, 14 nm) for sub-100 GHz. InP for > 100 GHz. Advantages: smallest size (single die, often < 5 × 5 mm). Lowest interconnect loss (no chip-to-chip connections). Lowest per-unit cost at very high volumes (one chip vs multiple). Best for standard, high-volume products. Disadvantages: the entire system must be in one semiconductor process. Each process is optimized for one function: CMOS: best for digital/baseband (low power, high density). GaAs/GaN: best for PA (high power, high linearity). InP: best for LNA (lowest noise above 40 GHz). SoC forces design compromises (the PA is suboptimal in CMOS, the digital is suboptimal in GaAs). Development cost is very high ($5M-$50M for a custom mmWave SoC). Yield: one defect on the die kills the entire system. (2) System-in-Package (SiP): multiple die (each optimized in the best semiconductor process for its function) are assembled in a single package. Example: GaAs PA die + SiGe transceiver die + CMOS baseband die + LTCC substrate with embedded passives and antenna. Advantages: each die uses the optimal process (best performance for each function). Flexibility to swap die (upgrade the PA without redesigning the transceiver). Lower development cost (use existing die, design only the package/substrate). Higher yield (each die is tested before assembly). Disadvantages: larger than SoC (multiple die + substrate + interconnects). Higher interconnect losses (die-to-die connections via bond wires or flip-chip bumps). Higher per-unit cost at very high volumes (assembly of multiple die).

Category: Millimeter Wave Specific Challenges

Updated: April 2026

Product Tie-In: mmWave Components, Substrates, Packaging

SoC vs SiP at mmWave

The choice between SoC and SiP depends on the volume, performance requirements, and development budget. Both approaches are used in current mmWave products.

Technical Considerations

(1) 77 GHz automotive radar SoC: Texas Instruments AWR series. Integrates 3-4 TX, 4 RX, PLL, ADC, radar processing DSP on a single SiGe BiCMOS die. The SoC approach works because: automotive radar is extremely high volume (> 100M units/year across the industry), the performance requirements are well-defined (< 1 km range, limited bandwidth), and the cost target is aggressive (< $5 per module). (2) 60 GHz WiGig (802.11ad/ay) SoC: Qualcomm QCA6421. Integrates full 60 GHz transceiver + baseband on 28 nm CMOS. The digital-heavy modulation (OFDM) and baseband processing are efficiently implemented in CMOS, and the 60 GHz front end (PA, LNA, mixer) is feasible in advanced CMOS with adequate (though not optimal) performance. (3) Limitations: at frequencies above 100 GHz: SoC in CMOS becomes extremely challenging (f_T must be > 3× the operating frequency for adequate gain). InP is used for >100 GHz SoC but at much lower volumes and higher cost. For very high PA power (> 1 W at mmWave): GaN SoC is needed, but GaN does not support dense digital integration. SiP is mandatory when high power and complex digital are both needed.

Performance Analysis

(1) Heterogeneous integration: the SiP combines die from different semiconductor processes: RF die (GaAs, GaN, InP): PA, LNA, switch. Signal processing die (SiGe BiCMOS): transceiver, frequency synthesizer, ADC/DAC. Digital die (CMOS): baseband, control, calibration. Passive substrate (LTCC, organic, glass): interconnects, embedded filters, matching networks, antenna. (2) Interconnect methods within the SiP: flip-chip (preferred for mmWave): lowest parasitic, suitable for > 40 GHz. Wire bond: acceptable below 20 GHz, marginal at 28 GHz with compensation. Through-substrate vias (TSV, TGV): provide vertical interconnects through the substrate or interposer. (3) 5G mmWave SiP example: Qualcomm QTM525/527 antenna module for 5G smartphones. Contains: Qualcomm transceiver IC (SiGe). GaAs PA and LNA die. Phase shifter ICs. Organic substrate with embedded antenna array (4 × 1 patch antenna). The module provides a complete 28/39 GHz front end in a compact package that mounts on the phone PCB.

Performance verification: confirm specifications against the application requirements before finalizing the design
Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades

Design Guidelines

(1) Choose SoC when: volume > 1M units/year (amortizes the high NRE). All functions can be implemented in one semiconductor process without critical performance compromises. Size is the primary constraint (wearables, IoT sensors). Standard product with minimal customization. (2) Choose SiP when: the system requires mixed semiconductor technologies (GaN PA + CMOS digital). Volume is moderate (10K-1M units/year). Multiple product variants are needed (different PA power levels, different frequency bands) using common die but different package configurations. Time-to-market is critical (reuse existing die). Performance optimization is more important than size minimization. (3) Emerging approach: chiplet architecture. Small, standardized die (chiplets) are assembled on an advanced interposer using high-density interconnects (microbumps at 40-100 um pitch). This combines the per-function optimization of SiP with the interconnect density approaching SoC. Active development by Intel (EMIB), TSMC (CoWoS), and academic research for mmWave and sub-THz applications.

Common Questions

Frequently Asked Questions

Which approach is used for 5G mmWave in smartphones?

SiP. The Qualcomm QTM525/527/545 modules are SiP designs with multiple die on an organic substrate: transceiver (SiGe), PA/LNA (GaAs), phase shifters, and antenna array (on the substrate). Samsung and MediaTek use similar SiP approaches. The SiP architecture allows: optimized PA in GaAs (higher power, better linearity than CMOS), compact transceiver in SiGe (excellent mixer and synthesizer performance), and integrated antenna on the organic substrate (AiP). Each phone contains 2-4 of these SiP modules pointed in different directions for beam diversity. The SiP approach was chosen over SoC because: no single semiconductor process provides the best performance for all functions at 28/39 GHz, and the antenna integration requires a low-loss substrate (organic) that cannot be the semiconductor die.

What about radar-on-chip?

Automotive radar (77 GHz) is one of the most successful SoC examples: TI AWR series, NXP TEF series, Infineon RXS series. These SoCs integrate the entire radar (TX, RX, synthesizer, ADC, DSP) on a single die. The SoC approach works for radar because: the PA power requirement is low (10-13 dBm, < 100 mW; adequate in SiGe BiCMOS), the LNA NF requirement is moderate (5-8 dB; SiGe is adequate), the processing is relatively simple (FFT-based range-Doppler), and the volume is extremely high (> 100M/year). For higher-performance radar (military, aerospace): SiP is used because the PA power (> 1 W), NF (< 3 dB), and processing requirements exceed SoC capabilities. GaAs/GaN PA + InP LNA + FPGA processor in a SiP package.

How do I estimate the cost of SoC vs SiP?

SoC cost model: NRE (non-recurring engineering): $5M-50M (mask set: $2M-10M for advanced CMOS; design: $3M-40M). Die cost: die_area × wafer_cost / (die_per_wafer × yield). For a 10 mm² die in 28 nm CMOS: die cost ≈ $2-5. Package: $0.50-2.00 (standard QFN or WLP). Total unit cost: $3-7 at high volume. SiP cost model: each die is purchased or fabricated separately (lower NRE per die, $0.5M-5M total). Assembly cost: $1-5 (die attach, wire bond/flip-chip, substrate fabrication). Package/substrate: $2-10 (LTCC or organic with embedded antenna). Total unit cost: $10-30 at moderate volume. The crossover: SoC becomes cheaper than SiP at volumes above approximately 500K-2M units (where the high NRE is amortized).

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