How do I design a cascode LNA using two transistors for improved gain and isolation?

Designing a cascode LNA using two transistors creates an amplifier with significantly higher gain and reverse isolation than a single common-source stage, while maintaining a noise figure close to the single-transistor minimum. The cascode consists of a common-source (CS) transistor as the input stage and a common-gate (CG) transistor as the output stage, with the CS drain connected directly to the CG source. The design involves: selecting the transistors (both transistors are typically from the same process; the CS transistor is selected for the lowest noise figure at the operating frequency; the CG transistor can be the same device or a slightly smaller device, since its noise contribution is reduced by the CS stage's gain), biasing the CS transistor for minimum noise figure (the gate bias sets the drain current to the optimum noise current I_opt; for GaAs pHEMTs: typically 10-15% of I_dss; for SiGe HBTs: the collector current for minimum NF, typically 1-5 mA), biasing the CG transistor (the CG gate is AC grounded through a bypass capacitor; the DC gate voltage is set to keep the transistor in saturation with the desired drain voltage; the CG transistor shares the same drain current as the CS transistor), designing the input matching network (match the input to the CS transistor's optimum noise impedance (Gamma_opt) for minimum noise figure; use inductive source degeneration for simultaneous noise and impedance matching: the source inductor creates a real impedance at the input (Rs_added = gm x L_s / C_gs) that can be designed to match 50 ohms while the input is conjugate-matched to Gamma_opt), designing the output matching network (match the output of the CG transistor for maximum power transfer to 50 ohms), and adding stability measures (the cascode is inherently more stable than a common-source, but stability must still be verified; add a series resistor on the CG gate bias line to suppress low-frequency oscillations).