Active Components

DDS + PLL Synthesizer

Q: How does a DDS-driven PLL reach a sub-Hz frequency step at microwave frequencies?

The DDS sets the loop reference. With an N-bit phase accumulator clocked at f_clk, the DDS frequency step is f_clk divided by 2 to the N. A 48-bit accumulator clocked at 500 MHz resolves about 1.8 microhertz at the DDS output. When that DDS output is used as the PLL reference, the loop divider N multiplies both the carrier and the step. So even with a multiplication of 100 the effective step at a 20 GHz output is still in the microhertz to millihertz range, far finer than an integer-N PLL whose step equals the reference frequency divided by the modulus. The DDS provides the resolution and the PLL provides the frequency reach and spectral purity.

Q: How do you set the PLL cleanup-loop bandwidth to suppress DDS spurs?

The dominant DDS spurs come from phase-accumulator truncation and DAC nonlinearity, and they typically fall at offsets from tens of kilohertz to several megahertz from the carrier. A narrow PLL loop, with a loop bandwidth set roughly 5 to 20 times below the lowest DDS spur offset of concern, acts as a tracking filter: the VCO follows the DDS phase inside the loop bandwidth and is filtered by the VCO free-running phase noise outside it. A common rule is to place the loop bandwidth at the crossover where DDS reference phase noise and multiplied VCO noise are equal, often 10 to 100 kHz. Too wide and the DDS spurs and quantization floor pass through; too narrow and VCO phase noise and slow settling dominate.

Q: What phase noise penalty does the PLL multiplication add to the DDS reference?

Inside the loop bandwidth the output tracks the reference, and frequency multiplication by N degrades phase noise by 20 times log of N decibels. Multiplying a DDS reference by 100 adds about 40 dB; multiplying by 1000 adds 60 dB. So a DDS reference at minus 150 dBc per hertz at 1 kHz offset, multiplied to 20 GHz with N of 100, lands near minus 110 dBc per hertz before adding charge-pump and divider noise. This is why the DDS clock and the PLL reference path must be very clean, and why hybrid designs often use a low division ratio with an offset mixer rather than a single large multiplication.

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Pairing two complementary frequency-generation methods, this hybrid architecture lets a direct digital synthesizer supply a finely tunable reference or interpolated step while a phase-locked loop multiplies that signal up to microwave frequencies and filters it. The DDS contributes sub-Hz tuning resolution and microsecond hop speed; the PLL contributes high carrier frequency and a clean spectrum by acting as a narrow tracking filter on the DDS output. Because the loop bandwidth is set below the lowest significant DDS spur, the architecture reaches 10 to 50 GHz with spur levels of −70 to −90 dBc and resolution finer than 1 Hz, a combination neither block achieves alone.

Category: Active Components

Resolution: < 1 Hz

Typical Spurs: −70 to −90 dBc

Combining DDS Resolution With PLL Spectral Purity

A standalone direct digital synthesizer offers exceptional frequency resolution and near-instant frequency hopping, but its output is bounded by the Nyquist limit of its clock (practically about 40 percent of f_clk) and its spectrum carries truncation and DAC-related spurs at well-defined offsets. A standalone integer-N frequency synthesizer reaches tens of gigahertz with a clean carrier, but its step size equals the reference frequency divided by the loop modulus, forcing a trade between resolution and loop bandwidth. The hybrid combines them: the DDS sets the small, fine-grained part of the frequency plan and the PLL handles the coarse multiplication to the target band.

In the most common topology the DDS output serves directly as the PLL reference. The loop divider N then scales both the carrier and the DDS step, so a DDS resolving microhertz at its own output still resolves microhertz to millihertz after a multiplication of 100 to 1000. A second common topology places the DDS in the feedback path as an offset, so the loop locks the VCO to a sum or difference of a fixed reference and the DDS frequency. Either way, the PLL behaves as a tracking bandpass filter centered on the carrier: it follows the DDS phase inside the loop bandwidth and substitutes the VCO free-running noise outside it.

The central design decision is the cleanup-loop bandwidth. The DDS spurs that matter sit from tens of kilohertz to a few megahertz off carrier, so a loop bandwidth roughly 5 to 20 times below the lowest spur offset rejects them while still tracking the DDS for tuning and modulation. Setting it too wide passes the DDS quantization floor and spurs straight through to the output; setting it too narrow lets multiplied VCO phase noise and slow settling dominate. The optimum usually lands at the offset where DDS reference noise (multiplied by 20 log N) crosses the VCO phase-noise curve.

Governing Relationships

DDS output frequency:
f_DDS = FTW × f_clk / 2^N (FTW = frequency tuning word, N = accumulator bits)

Effective output step (DDS as PLL reference):
Δf_out = (f_clk / 2^N) × N_div

Multiplication phase-noise penalty (in loop):
L_out ≈ L_ref + 20·log₁₀(N_div) dBc/Hz

Cleanup-loop rule of thumb:
BW_loop ≈ f_{DDS,spur(min)} / 5 to / 20 (reject DDS spurs, track DDS tuning)

Example: f_clk = 500 MHz, N = 48 → DDS step ≈ 1.8 μHz. Running the DDS output at 100 MHz (0.2 × f_clk, below the practical Nyquist limit) and using N_div = 200 to reach a 20 GHz output gives Δf_out ≈ 355 μHz, and the multiplication adds ≈46 dB to the reference phase noise.

Architecture Comparison

Parameter	DDS only	Integer-N PLL	Fractional-N PLL	DDS + PLL hybrid
Resolution	< 1 Hz	f_ref / modulus	sub-Hz (with frac spurs)	< 1 Hz
Max output	~0.4 × f_clk	50+ GHz	50+ GHz	10 to 50 GHz
Phase noise @1 kHz	−145 to −155 dBc/Hz	set by 20 log N	set by 20 log N	−100 to −115 dBc/Hz
Spurious	−60 to −80 dBc	−80 to −90 dBc	−55 to −75 dBc	−70 to −90 dBc
Switching speed	< 1 μs	10 to 100 μs	10 to 100 μs	1 to 50 μs
Complexity / power	Low	Low	Moderate	High

Common Questions

Frequently Asked Questions

How does a DDS-driven PLL reach a sub-Hz frequency step at microwave frequencies?

The DDS sets the loop reference. With an N-bit accumulator clocked at f_clk, the DDS step is f_clk / 2^N; a 48-bit accumulator at 500 MHz resolves about 1.8 μHz. The loop divider N_div multiplies both the carrier and the step, so even at a 20 GHz output the effective step stays in the μHz to mHz range, far finer than an integer-N PLL whose step equals f_ref divided by the modulus. The DDS supplies resolution; the PLL supplies frequency reach and spectral purity.

How do you set the PLL cleanup-loop bandwidth to suppress DDS spurs?

The dominant DDS spurs come from phase-accumulator truncation and DAC nonlinearity and usually sit from tens of kHz to a few MHz off carrier. A loop bandwidth set roughly 5 to 20 times below the lowest spur of concern acts as a tracking filter: the VCO follows DDS phase inside BW_loop and is filtered outside it. Place BW_loop near the crossover (often 10 to 100 kHz) where DDS reference noise equals multiplied VCO noise. Too wide passes the spurs; too narrow lets VCO noise and slow settling dominate.

What phase noise penalty does the PLL multiplication add to the DDS reference?

Inside the loop bandwidth the output tracks the reference, and multiplication by N_div degrades phase noise by 20·log(N_div) dB: 40 dB for ×100, 60 dB for ×1000. A DDS reference at −150 dBc/Hz at 1 kHz multiplied to 20 GHz with N_div = 100 lands near −110 dBc/Hz before charge-pump and divider noise. That is why hybrids favor a low division ratio with an offset mixer over a single large multiplication, and demand a very clean DDS clock.

Related Terms

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