Power Electronics

Cross-Conduction

Q: How much dead-time does a GaN half-bridge need to avoid cross-conduction?

Far less than a silicon MOSFET stage. GaN HEMTs have very small gate charge (Qg of 5 to 10 nC) and no slow minority-carrier reverse recovery, so they turn off quickly and the dead-time can be as short as 5 to 20 ns. Silicon superjunction MOSFETs in a totem-pole power-factor-correction leg often need 100 to 400 ns of dead-time because of their larger gate charge and reverse-recovery tail. Setting dead-time too long is not free: during the dead interval the inductor current flows through the body diode or the reverse channel of the off device, and GaN reverse conduction has a high effective forward drop of 1.5 to 3 V, so excess dead-time adds conduction loss. Designers tune dead-time to the minimum value that still guarantees the turning-off device has fully blocked before its complement turns on, with a small margin for temperature and part-to-part variation.

Q: What causes cross-conduction even when dead-time is set correctly?

Induced or dynamic turn-on of the supposedly off device. When the high-side switch turns on, the switch node slews at 50 to 150 V/ns in fast GaN designs. That dv/dt couples current through the off device's drain-to-gate Miller capacitance (Crss) into its gate. If the gate driver pull-down impedance and the gate loop inductance cannot hold the gate below threshold, the device partially turns on and a shoot-through pulse flows even though the gate command was low. The fix is a low-impedance pull-down (often a separate sink path or a negative off-bias of minus 2 to minus 4 V for GaN), minimized common-source inductance, and a tight gate loop. Layout parasitics, not just timing, decide whether a leg cross-conducts at high dv/dt.

Q: How is shoot-through current measured or detected on the bench?

The classic method is a current-viewing resistor or a high-bandwidth Rogowski coil in series with the half-bridge rail decoupling path, captured on an oscilloscope synchronized to the gate drive edges. A clean leg shows only the capacitive charging spike of the switch node; a cross-conducting leg shows an additional current pulse during the transition that does not deliver energy to the load. On a power analyzer the symptom is excess input power and device heating that scale with switching frequency rather than load current. In production, designers monitor case temperature rise at no load: a leg that runs hot with no output current is almost always shoot-through or excessive dead-time reverse conduction.

/kraws kon-duhk-shuhn/

A fault condition in which the high-side and low-side switches of a half-bridge leg conduct at the same time for a brief instant during a switching transition, momentarily shorting the supply rail to ground through both devices. Also called shoot-through, this overlap draws a large current spike that delivers no energy to the load, dissipating it instead as heat in the switches and adding to the loss budget of a switching regulator. It is suppressed by inserting dead-time, a deliberate blanking interval between the turn-off of one device and the turn-on of its complement. In fast GaN HEMT stages used for RF supply rails and Class-D power amplifiers, high dv/dt at the switch node can also induce shoot-through through Miller coupling even when the timing is correct.

Category: Power Electronics

GaN dead-time: 5 to 20 ns

Si dead-time: 100 to 400 ns

Why Two Switches in One Leg Cannot Overlap

Every half-bridge or totem-pole stage stacks two switches in series between the supply rail and return, with their shared midpoint forming the switch node that drives the load. Normal operation alternates them: when the high-side device is on, the low-side is off, and vice versa. Cross-conduction occurs in the sliver of time when the second device begins conducting before the first has finished blocking. Because both then present a low channel resistance, the bridge briefly becomes a direct short across the bus capacitor. The resulting current is limited only by the device on-resistance and the loop inductance, so it can spike to tens or hundreds of amps in a 48 V rail before either gate finishes transitioning.

The current does no useful work. It circulates from the bus capacitor through both switches and back, depositing its energy as heat in the channels. At low switching frequency a small amount of overlap may be tolerable, but switching loss from shoot-through scales linearly with frequency, so the megahertz-rate converters that feed RF power amplifier rails and envelope-tracking modulators cannot afford it. Left uncontrolled, repetitive shoot-through raises junction temperature, erodes efficiency, and can drive a device into thermal runaway. The cure is to never command both gates on together, and to guarantee the off device stays off through the transition.

Dead-Time and the Overlap Budget

Dead-time is the engineered gap that prevents overlap. The controller turns one device fully off, waits a blanking interval, then turns the other on. The interval must exceed the worst-case turn-off delay of the outgoing switch, which is set by its gate charge, the gate driver sink current, and the gate loop inductance. The trade is direct: too little dead-time risks cross-conduction, while too much forces load current to free-wheel through a body diode or a reverse-conducting GaN channel, both of which have a high forward drop that wastes energy. The optimum is the smallest blanking time that still clears the transition with margin over temperature and part spread.

dv/dt Induced Turn-On

Even with correct timing, a fast switch node can re-trigger the off device. As the complementary switch turns on, the node slews at 50 to 150 V/ns in aggressive GaN layouts. That slew couples a current through the off device drain-to-gate capacitance, and if the gate driver cannot sink it the gate voltage rises toward threshold and the device partially turns on, producing a shoot-through pulse. A low-impedance pull-down, a negative off-bias for GaN, and a tight gate loop with minimal common-source inductance are the standard defenses.

Governing Relations

Minimum dead-time (turn-off must complete first):
t_dead > t_off,delay + (Q_g,off × R_g) / (V_drive − V_th)

Shoot-through energy per event:
E_ST ≈ ½ × V_bus × I_ST,peak × t_overlap

Shoot-through power loss:
P_ST = E_ST × f_sw (two events per cycle)

dv/dt induced gate rise (Miller):
V_gs,ind ≈ (dv/dt) × C_rss × R_g,off < V_th required

Where Q_g = gate charge, R_g = gate resistance, V_th = threshold, V_bus = rail voltage, C_rss = reverse transfer capacitance, f_sw = switching frequency. Example: 48 V bus, 60 A peak, 4 ns overlap, 1 MHz → E_ST ≈ 5.8 μJ, P_ST ≈ 11.5 W per leg.

Dead-Time by Device Technology

Switch technology	Typical Q_g	Reverse recovery	Typical dead-time	Reverse drop in dead-time	Cross-conduction risk driver
GaN HEMT (e-mode)	5 to 10 nC	None (no body diode)	5 to 20 ns	1.5 to 3 V	High dv/dt Miller turn-on
Si superjunction MOSFET	50 to 150 nC	Slow, large Q_rr	100 to 400 ns	0.7 to 1 V (body diode)	Reverse recovery charge
SiC MOSFET	30 to 90 nC	Moderate	50 to 150 ns	2 to 4 V (body diode)	Recovery + high dv/dt
Si IGBT	100 to 400 nC	Tail current	1 to 4 µs	1.5 to 2.5 V	Turn-off tail current

Common Questions

Frequently Asked Questions

How much dead-time does a GaN half-bridge need to avoid cross-conduction?

Far less than silicon. GaN HEMTs have small gate charge (Q_g of 5 to 10 nC) and no minority-carrier reverse recovery, so dead-time can be 5 to 20 ns. Silicon superjunction MOSFETs in a totem-pole leg often need 100 to 400 ns. Too much dead-time is not free: load current then flows through the reverse channel, and GaN reverse conduction has a 1.5 to 3 V drop, adding loss. Tune to the minimum that clears the transition with margin.

What causes cross-conduction even when dead-time is set correctly?

dv/dt induced turn-on of the off device. As the complement turns on, the switch node slews at 50 to 150 V/ns in fast GaN designs. That slew couples current through the off device drain-to-gate capacitance (C_rss); if the driver pull-down cannot hold the gate below threshold, the device partially turns on and shoot-through flows. Fixes: low-impedance pull-down, negative off-bias of −2 to −4 V for GaN, and minimal common-source inductance.

How is shoot-through current measured or detected on the bench?

Use a current-viewing resistor or a high-bandwidth Rogowski coil in the rail decoupling path, captured on a scope synced to the gate edges. A clean leg shows only the capacitive switch-node spike; a cross-conducting leg shows an extra pulse during the transition that delivers no load energy. On a power analyzer the tell is excess input power and heating that scale with frequency, not load current. In production, watch case temperature rise at no load.

Related Terms

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