Power Electronics

Dead Time

Q: How do you calculate the minimum required dead time for a half-bridge?

The minimum dead time must exceed the worst-case turn-off delay of the outgoing switch plus the propagation skew between the two gate-driver channels, with margin for temperature and gate-resistor tolerance. A practical estimate is t_dead(min) = t_off(max) - t_on(min) + t_skew + t_margin. For a 650 V silicon superjunction MOSFET with roughly 60 ns turn-off and 20 ns turn-on, plus 10 ns of driver matching skew, a designer typically sets 80 to 120 ns. Wide-bandgap GaN HEMTs switch far faster, so dead times of 10 to 30 ns are common. Always validate at the highest junction temperature, because turn-off delay grows as the device heats up.

Q: Why does excessive dead time increase converter losses?

During dead time the load current must freewheel through the body diode (or, in GaN, the reverse-conduction channel) of the off-going synchronous device. A silicon MOSFET body diode drops about 0.8 to 1.0 V, while a GaN device in reverse conduction can drop 2 to 4 V because there is no true PN body diode. Conduction loss during dead time equals V_diode times I_load times 2 times t_dead times f_sw per cycle, so it scales directly with both dead-time duration and switching frequency. At 500 kHz with 20 A load and 100 ns excess dead time, an extra 1 V drop wastes roughly 2 W per phase. Excessive dead time also injects voltage distortion into motor-drive and inverter output waveforms.

Q: What is dead-time distortion in a PWM inverter and how is it compensated?

Because both switches are off during dead time, the inverter output voltage is determined by the direction of the load current rather than the PWM command, producing a small volt-second error every switching cycle. This accumulates into low-order harmonics (5th, 7th) and a fundamental-voltage error that is most visible at low modulation indices, causing torque ripple in motor drives. Compensation adds or subtracts a corrective volt-second pulse based on the sign of the measured phase current, effectively pre-distorting the duty cycle. Feedforward compensation and current-polarity detection near zero crossing are the common methods.

/ded tym/

A short, deliberately inserted interval during which both transistors in a half-bridge leg are commanded off at the same time, guaranteeing that the outgoing switch has fully stopped conducting before the complementary device begins to turn on. This blanking window prevents shoot-through, the brief but destructive cross-conduction current that would otherwise flow straight across the DC bus when both switches conduct together. Power-supply and motor-drive designers set dead time in their gate driver or PWM modulator, balancing it against the duty cycle so it is long enough for safety yet short enough to limit body-diode conduction loss. Typical values range from 10 to 30 ns for fast GaN HEMTs up to 80 to 500 ns for high-voltage silicon IGBT bridges.

Category: Power Electronics

Typical Range: 10 ns to 500 ns

Primary Role: Shoot-through prevention

Why Switching Bridges Need a Blanking Window

Every half-bridge pairs a high-side and a low-side switch whose gate signals are nominally complementary: when one is commanded on, the other is commanded off. Real transistors, however, do not switch instantaneously. The outgoing device has a finite turn-off delay set by its gate charge, the Miller plateau, and the gate-drive pull-down resistance, while the incoming device begins conducting after its own turn-on delay. If the controller simply inverted one PWM signal to drive the other gate, the slower turn-off of one switch would overlap the faster turn-on of its partner, momentarily shorting the DC link. The resulting current spike can reach hundreds of amps, destroy the devices, or at minimum spike junction temperature and erode reliability.

Dead time solves this by holding both gates low for a fixed interval at every commutation. During that window the inductor or load current cannot disappear, so it freewheels through the body diode of the off-going synchronous MOSFET, through a GaN device in reverse conduction, or through an antiparallel diode across an IGBT. The interval must comfortably exceed the worst-case sum of the outgoing switch turn-off delay and the channel-to-channel propagation skew between the two driver outputs, with extra margin for the longer delays seen at high junction temperature.

The penalty is efficiency and waveform fidelity. Conduction through a body diode dissipates more than channel conduction would, and in GaN parts the reverse drop of 2 to 4 V is especially costly because there is no true PN junction diode. Dead time also creates a volt-second error each cycle whose sign follows the load-current direction, producing the low-order harmonics known as dead-time distortion in inverter outputs. Good designs therefore tune dead time as tightly as the device timing and driver matching safely allow, sometimes adapting it dynamically with load and temperature.

Governing Timing Relationships

Minimum required dead time:
t_dead(min) ≈ t_off(max) − t_on(min) + t_skew + t_margin

Dead-time conduction loss per leg:
P_dt ≈ V_diode × I_load × 2 × t_dead × f_sw

Output volt-second error (per cycle):
ΔV_out = ± V_bus × (t_dead × f_sw) (sign follows i_load)

Where t_off/t_on = switch delays, t_skew = driver channel mismatch, V_diode ≈ 0.8 V (Si body diode) or 2 to 4 V (GaN reverse), f_sw = switching frequency. Example: V_diode=1 V, I_load=20 A, t_dead=100 ns, f_sw=500 kHz → P_dt ≈ 2 W per leg.

Dead Time by Switch Technology

Switch Type	Typical Dead Time	Reverse-Conduction Drop	Switching Frequency	Key Concern
GaN HEMT	10 to 30 ns	2 to 4 V (no body diode)	500 kHz to 3 MHz	Minimize dead time; reverse loss high
SiC MOSFET	20 to 80 ns	2 to 4 V (intrinsic) / 0.8 V (SBD)	50 to 500 kHz	Add Schottky to cut reverse loss
Si superjunction MOSFET	50 to 150 ns	~0.8 to 1.0 V	50 to 300 kHz	Slow body-diode recovery
Si IGBT	200 to 500 ns	~1.5 to 2.5 V (antiparallel diode)	2 to 20 kHz	Long tail current, hot turn-off

Common Questions

Frequently Asked Questions

How do you calculate the minimum required dead time for a half-bridge?

Size it to exceed the worst-case turn-off delay of the outgoing switch plus the gate-driver channel skew, with margin: t_dead(min) ≈ t_off(max) − t_on(min) + t_skew + t_margin. A 650 V silicon superjunction MOSFET (~60 ns off, ~20 ns on, ~10 ns skew) typically lands at 80 to 120 ns, while fast GaN HEMTs need only 10 to 30 ns. Always validate at maximum junction temperature, where turn-off delay lengthens.

Why does excessive dead time increase converter losses?

While both switches are off, load current freewheels through the body diode or reverse-conduction channel of the off-going device. A Si body diode drops ~0.8 to 1.0 V; a GaN device in reverse conduction drops 2 to 4 V. Loss scales as V_diode × I_load × 2 × t_dead × f_sw, so at 500 kHz with 20 A and 100 ns excess dead time an extra 1 V wastes roughly 2 W per leg.

What is dead-time distortion in a PWM inverter and how is it compensated?

With both switches off, the output voltage follows the load-current polarity rather than the PWM command, creating a small volt-second error each cycle. This builds into 5th and 7th harmonics and a fundamental error worst at low modulation index, causing motor-drive torque ripple. Compensation adds or subtracts a corrective volt-second pulse based on the measured current sign, effectively pre-distorting the duty cycle near each zero crossing.

Related Terms

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