RF Design

Controlled Impedance

Q: What trace width gives 50 ohms on a typical RF board?

It depends on the dielectric thickness and permittivity. On a microstrip with a 10 mil (0.254 mm) FR-4 substrate of relative permittivity 4.3, a single trace needs roughly 18 to 19 mil width for 50 ohms. On thin RF laminate such as Rogers RO4350B (Er 3.66) at 10 mil, the width is about 20 mil because the lower permittivity widens the conductor. Halving the dielectric thickness roughly halves the required trace width. Because impedance scales with the ratio of width to height, designers fix the stackup first, then solve for width using a 2D field solver or a closed-form microstrip equation. A grounded coplanar waveguide adds side ground gaps as a second tuning knob, which is why most RF boards use it instead of plain microstrip.

Q: What tolerance can a fabricator hold on controlled impedance?

Standard controlled-impedance fabrication holds plus or minus 10 percent, so a 50 ohm trace lands between 45 and 55 ohms. Premium RF processes with TDR verification on a test coupon can hold plus or minus 5 percent (47.5 to 52.5 ohms). The error budget comes from etch variation (trace width tolerance of plus or minus 0.5 to 1 mil), dielectric thickness variation of plus or minus 10 percent on FR-4 (tighter on bonded RF laminates), copper roughness, and solder-mask coverage, which can lower microstrip impedance by 1 to 3 ohms. Each fabricated panel includes an impedance coupon that the fab measures with a time-domain reflectometer and reports against the target on the fab drawing.

Q: Does solder mask change microstrip impedance?

Yes. A solder-mask layer over a microstrip trace adds a thin high-permittivity dielectric (Er around 3.3 to 3.9, typically 0.5 to 1 mil thick) above and beside the conductor, which increases the effective permittivity and lowers the characteristic impedance by roughly 1 to 3 ohms compared with the bare-copper case. RF designers either model the mask explicitly in the field solver or specify mask-free (exposed copper) over impedance-critical traces. Stripline buried between two ground planes is immune to this effect, which is one reason high-precision controlled-impedance routing often uses stripline despite its higher loss and harder rework.

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Holding a transmission structure to a known target value is the goal here: a PCB trace or cable is dimensioned and stacked up so its characteristic impedance stays at a specified figure, almost always 50 Ω in RF work, within a tight tolerance. The impedance is set by conductor width, dielectric thickness, and the substrate permittivity, so the fabricator fixes the layer stackup and then solves for trace width. Because the value is fixed rather than left to chance, signals see a matched path with minimal reflection, which is essential for impedance matching across RF and high-speed digital interconnects. Typical fabrication holds ±10%, with premium RF processes reaching ±5% verified by time-domain reflectometry on a panel coupon.

Category: RF Design

Target Z₀: 50 Ω (typ.)

Tolerance: ±5% to ±10%

How Trace Geometry Sets Z₀

A transmission line on a circuit board behaves as a distributed network of series inductance and shunt capacitance per unit length. Its characteristic impedance is the square root of that inductance-to-capacitance ratio, which means the value is governed entirely by physical geometry and the surrounding dielectric, not by the line length or the source. Widen the trace and the shunt capacitance to the reference plane rises while the loop inductance falls, so the impedance drops. Move the trace farther from the plane (thicker dielectric) and the impedance climbs. Controlled-impedance design is the discipline of pinning these geometric variables so that every impedance-critical net lands on the target value across the whole panel.

The dominant structures are microstrip, a trace on an outer layer above a single ground plane, and stripline, a trace buried between two ground planes. Microstrip is easier to route and probe but its field straddles both the substrate and the air above it, so its effective permittivity is a weighted average that shifts when solder mask is added. Stripline sits in a homogeneous dielectric, giving a cleaner, mask-immune impedance and slightly slower propagation. For RF boards the most common choice is grounded coplanar waveguide, a microstrip variant with adjacent ground pours that give the designer a second geometric knob (the gap) for hitting 50 Ω while suppressing surface-wave coupling.

Material selection matters as much as geometry. FR-4 has a relative permittivity near 4.3 that drifts with frequency and resin content, which limits its accuracy above a few gigahertz, so millimeter-wave assemblies move to PTFE-based laminates such as Rogers RO4350B or RT/duroid, where the permittivity is tightly specified. The fabricator verifies the result with a time-domain reflectometer on a dedicated impedance coupon and reports the measured value against the target on the fab drawing.

Microstrip and Stripline Impedance Equations

Characteristic Impedance (lossless line):
Z₀ = √(L / C) ≈ √(L₀ / C₀) per unit length

Microstrip (IPC-2141 / Wheeler approximation, 0.1 < W/h < 2):
Z₀ ≈ (87 / √(ε_r + 1.41)) × ln(5.98h / (0.8W + t)) Ω

Symmetric Stripline (thin trace):
Z₀ ≈ (60 / √ε_r) × ln(4b / (0.67π(0.8W + t))) Ω

Where W = trace width, t = copper thickness, h = dielectric height above the plane, b = plate separation (stripline), ε_r = relative permittivity. Example: microstrip, ε_r = 3.66 (RO4350B), h = 10 mil, t = 0.6 mil → the equation gives Z₀ ≈ 50 Ω at W ≈ 20 mil (W/h = 2.0).

Stackup and Geometry Comparison

Structure	Reference	50 Ω Width (10 mil h)	Mask Sensitive	Loss	Best Use
Microstrip (FR-4)	1 plane	~18 mil	Yes (1 to 3 Ω)	Moderate	Low-cost RF, sub-6 GHz
Microstrip (RO4350B)	1 plane	~20 mil	Yes	Low	mmWave front ends
Grounded CPW	1 plane + side pours	Set by gap + width	Reduced	Low	Dense RF routing
Symmetric stripline	2 planes	~9 mil (b = 20 mil)	No	Higher	High-precision digital/RF
Differential pair	1 to 2 planes	100 Ω diff (gap-set)	Yes (microstrip)	Moderate	SerDes, LVDS, USB

Common Questions

Frequently Asked Questions

What trace width gives 50 ohms on a typical RF board?

It depends on the stackup. On microstrip over 10 mil FR-4 (ε_r ≈ 4.3) a single trace needs roughly 18 to 19 mil for 50 Ω; on 10 mil RO4350B (ε_r 3.66) it widens to about 20 mil because the lower permittivity demands a wider conductor. Halving the dielectric height roughly halves the width. Fix the stackup first, then solve for W with a 2D field solver or the microstrip closed form. Grounded coplanar waveguide adds the ground gap as a second tuning knob.

What tolerance can a fabricator hold on controlled impedance?

Standard fabrication holds ±10%, so a 50 Ω trace lands between 45 and 55 Ω. Premium RF processes with TDR-verified coupons hold ±5% (47.5 to 52.5 Ω). The error budget comes from etch variation (±0.5 to 1 mil on width), dielectric thickness spread of ±10% on FR-4, copper roughness, and solder mask. Each panel carries an impedance coupon the fab measures and reports against the target.

Does solder mask change microstrip impedance?

Yes. A 0.5 to 1 mil mask layer (ε_r ≈ 3.3 to 3.9) over a microstrip trace raises the effective permittivity and lowers Z₀ by roughly 1 to 3 Ω versus bare copper. Designers either model the mask in the field solver or specify exposed copper over impedance-critical traces. Buried stripline is immune, which is one reason high-precision controlled-impedance routing favors stripline despite higher loss and harder rework.

Related Terms

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