Wireless System Design

Control Interface

Q: Should I use SPI or I2C for an RF control interface?

SPI is the default choice for RF devices that need fast, low-latency updates, such as frequency synthesizers retuned on a hop-by-hop basis. A 3-wire or 4-wire SPI bus running at 10 to 50 MHz writes a typical 24-bit or 32-bit register in well under 1 microsecond, and a dedicated chip-select line per device avoids address collisions. I2C uses only two wires (SCL and SDA) and its 7-bit address space holds 128 addresses, of which 16 are reserved, so up to 112 devices share a single bus, which saves pins when many slow-changing devices (temperature sensors, EEPROMs, bias DACs) share a board. The trade-off is speed: standard-mode I2C is 100 kHz and fast-mode is 400 kHz, so writing the same 32-bit register takes roughly 100 microseconds. Use SPI when retune latency dominates and I2C when pin count and device fan-out dominate.

Q: How fast can a control interface retune an RF synthesizer?

Total retune latency is the sum of the register-write time over the control bus plus the PLL lock time. The bus-write portion for a fractional-N synthesizer is one to four 32-bit SPI transfers; at a 20 MHz SPI clock that is about 1.6 microseconds per register, so 3 to 6 microseconds total. The PLL lock time then dominates, typically 10 to 100 microseconds for a loop bandwidth of 50 to 200 kHz. Many modern synthesizers add a register FIFO or fast-lock mode that widens the loop during acquisition, cutting lock time to under 20 microseconds. For frequency-hopping radars and agile communications, designers minimize the control-bus contribution by writing only the registers that change rather than reprogramming the full register map.

Q: What causes glitches when writing an attenuator or switch over a control interface?

Glitches come from non-atomic register updates and from the device acting on intermediate bus states. A parallel GPIO-controlled attenuator changes one bit at a time, so a transition from 15 dB to 16 dB can momentarily pass through 31 dB if the most-significant bit settles before the others. Devices with a latch-enable (LE) or load pin avoid this by shifting the full word in first and asserting LE to update all bits simultaneously. On I2C, an interrupted transaction can leave a half-written register; using a single block write and verifying with a read-back guards against it. Adding 100 pF of bypass on control lines and respecting the device setup and hold times (often 2 to 10 ns) eliminates the remaining timing-related glitches.

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Within an RF subsystem, the digital bus and register map through which a host processor configures and monitors active components is known as the control interface. Implemented most often over SPI, I2C, or a bank of parallel GPIO lines, it programs synthesizer frequency, attenuator state, amplifier bias, and switch position, and reads back lock-detect and temperature flags. In a software-defined radio or a multi-chip transceiver architecture, the control interface is the boundary between the baseband firmware and the analog front end, and its bandwidth and latency directly bound how quickly a system can retune, switch bands, or run automatic gain control loops.

Category: Wireless System Design

Common Buses: SPI, I2C, GPIO

Typical Clock: 100 kHz to 50 MHz

How RF Devices Are Programmed

Almost every modern RF device with a tunable parameter exposes a control interface so that firmware, not jumpers or trim pots, sets its behavior. A frequency synthesizer carries a register map that holds the integer-N and fractional-N divider values, charge-pump current, and output divider; a digital step attenuator holds an attenuation code; a variable-gain amplifier holds a gain word; an RF switch holds a port-select code. The host writes these registers over a serial or parallel bus, and the device latches the new value into its analog hardware. The choice of physical layer (SPI, I2C, or parallel GPIO) is a system-level decision that trades pin count against speed and against the ability to address many devices on one bus.

SPI dominates fast-changing RF control because it is full-duplex, has no addressing overhead, and clocks at tens of megahertz. A four-wire SPI link (SCLK, MOSI, MISO, and a per-device chip-select) shifts a 24-bit or 32-bit word into the device most-significant-bit first; asserting a latch-enable line then updates all bits at once, which is the key to glitch-free attenuator and synthesizer writes. I2C trades speed for wiring: two open-drain lines (SCL and SDA) carry a 7-bit device address plus data, letting dozens of slow housekeeping parts share the same pair. Parallel GPIO is the simplest and lowest-latency option for a handful of bits, common on coarse RF switches and PIN-diode attenuators where one pin equals one state.

Latency matters because the control interface sits in the critical path of any agile system. For a frequency-hopping radio, total retune time is the bus-write time plus the PLL lock time, and good firmware writes only the registers that change. For a fast AGC loop, the round-trip of reading a power-detector value and writing a new gain code sets the loop update rate. Designers therefore budget the control bus alongside the RF chain, not as an afterthought.

Control-Bus Timing and Latency

Register-write time (serial bus):
t_write ≈ N_bits / f_clk

Total retune latency (synthesizer):
t_retune = t_write + t_lock

Maximum AGC loop update rate:
f_update ≈ 1 / (t_read + t_compute + t_write)

Where N_bits = register length, f_clk = bus clock, t_lock = PLL lock time. Example: a 32-bit register over a 20 MHz SPI bus gives t_write ≈ 1.6 μs; with t_lock ≈ 30 μs, t_retune ≈ 32 μs. The same write over 400 kHz I2C takes ≈ 80 μs.

Physical-Layer Comparison

Interface	Wires	Clock Rate	32-bit Write Time	Addressing	Best RF Use
SPI (4-wire)	4 + 1 CS/device	10 to 50 MHz	≈ 0.6 to 3 μs	Per-device chip-select	Synthesizers, fast attenuators
SPI (3-wire)	2 + 1 CS/device	10 to 50 MHz	≈ 0.6 to 3 μs	Per-device chip-select	Pin-limited RFICs
I2C	2 shared	100 / 400 kHz / 1 MHz	≈ 32 to 320 μs	7-bit, up to 112 devices	Bias DACs, sensors, EEPROM
Parallel GPIO	1 per bit	Static / < 50 ns settle	n/a (direct)	None (point-to-point)	Coarse switches, PIN attenuators
JESD204B/C (data + sync)	Lanes + SYSREF	Multi-Gbps	n/a (SPI still configures)	Lane mapping, SYSREF align	High-channel-count data converters

Common Questions

Frequently Asked Questions

Should I use SPI or I2C for an RF control interface?

SPI is the default for devices needing fast, low-latency updates such as hop-by-hop synthesizer retuning; a 10 to 50 MHz bus writes a 32-bit register in well under 1 μs, and a per-device chip-select avoids address collisions. I2C uses two wires and its 7-bit address space (128 addresses, 16 reserved) holds up to 112 devices, saving pins for slow housekeeping parts, but at 100 to 400 kHz the same write takes around 80 μs. Choose SPI when retune latency dominates, I2C when pin count and fan-out dominate.

How fast can a control interface retune an RF synthesizer?

Total retune latency is the register-write time plus PLL lock time. Writing 3 to 6 registers at a 20 MHz SPI clock takes roughly 3 to 6 μs, after which the PLL lock time (10 to 100 μs for a 50 to 200 kHz loop) dominates. Fast-lock modes that widen the loop during acquisition can cut lock time below 20 μs. Agile systems minimize the bus contribution by writing only the registers that actually change.

What causes glitches when writing an attenuator or switch over a control interface?

Glitches arise from non-atomic updates: a parallel-controlled attenuator changing 15 dB to 16 dB can briefly pass through 31 dB if the MSB settles first. A latch-enable (LE) pin fixes this by shifting the full word in, then updating all bits at once. On I2C, a single block write plus read-back guards against half-written registers. Respecting the 2 to 10 ns setup and hold times and bypassing control lines with 100 pF removes the rest.

Related Terms

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