CompactPCI
Understanding CompactPCI
CompactPCI, abbreviated cPCI, was introduced by the PCI Industrial Computer Manufacturers Group (PICMG) in 1997 to bring the proven PCI bus protocol into a packaging that could survive industrial, military, and telecom environments. Electrically it is the same parallel, multiplexed address and data bus used in desktop computers of that era, so device drivers, bridge silicon, and operating-system support transferred directly. Mechanically, however, it abandons the fragile horizontal edge-card slot of a PC motherboard in favor of vertical Eurocards held by metal ejector handles and seated into a robust pin-and-socket connector. This combination of software familiarity and mechanical ruggedness made cPCI a dominant platform for embedded RF and signal-processing subsystems for well over a decade.
Form Factor and Connector
Cards follow the IEEE 1101 Eurocard sizes: 3U boards measure 100 mm by 160 mm and 6U boards measure 233.35 mm by 160 mm. The defining feature is the 2mm hard-metric connector specified in IEC 61076-4-101, a press-fit pin-and-socket interface with controlled impedance and gas-tight contacts. A 3U board uses connectors J1 and J2; a 6U board adds J3 through J5, providing up to 220 contacts for additional bus signals, rear I/O, and user-defined pins. Because contact is made on multiple redundant pins rather than a single gold finger, the connection resists fretting corrosion and intermittent opens under vibration, which is essential when an RF receiver card must hold calibration on a moving platform.
Backplane, Bus Loading, and Hot Swap
The CompactPCI backplane is passive: it carries the bus traces and power but contains no active logic, so it is highly reliable and easy to replace. A single 32-bit or 64-bit segment supports up to 8 slots, one designated as the system slot that hosts the host bridge and arbiter, and the rest as peripheral slots. To exceed 8 cards, integrators add PCI-to-PCI bridge boards that create additional bus segments. The PICMG 2.1 Hot Swap specification allows individual cards to be inserted or removed while the system runs, using staged-length pins and a microswitch in the ejector handle so power and the bus are connected in a safe order. For RF systems this means a failed downconverter or processor card can be exchanged without taking the whole chassis offline.
Role in RF and Signal-Processing Systems
In a typical software-defined radio or radar back end, the RF front end downconverts and digitizes the signal, then the data flows into a CompactPCI chassis where FPGA or DSP cards perform filtering, demodulation, and detection. cPCI provides the slot-to-slot data path, the system timing distribution, and the management interface. The bottleneck of classic parallel CompactPCI is bandwidth: a 64-bit, 66 MHz bus tops out near 528 MB/s shared across all cards, which is modest for wideband instantaneous-bandwidth receivers. This limitation is why switched-serial successors such as VPX and CompactPCI Serial were developed, replacing the shared parallel bus with point-to-point PCI Express, Ethernet, and SerDes links while keeping the rugged Eurocard mechanics.
Bus Throughput
BWpeak = (W / 8) × fclk
Worked example (64-bit, 66 MHz):
BWpeak = (64 / 8) × 66 × 106 = 528 MB/s (shared)
Where W = bus width in bits (32 or 64), fclk = bus clock in Hz (33 MHz or 66 MHz). The result is the theoretical aggregate burst rate shared by every card on the segment; sustained throughput is lower due to arbitration, address phases, and wait states. Dividing by 8 converts bits per second to bytes per second.
CompactPCI Bus Variants
| Configuration | Bus Width | Clock | Peak Throughput (shared) | Max Cards / Segment |
|---|---|---|---|---|
| cPCI 32-bit / 33 MHz | 32-bit | 33 MHz | 132 MB/s | 8 |
| cPCI 32-bit / 66 MHz | 32-bit | 66 MHz | 264 MB/s | 4 to 5 |
| cPCI 64-bit / 33 MHz | 64-bit | 33 MHz | 264 MB/s | 8 |
| cPCI 64-bit / 66 MHz | 64-bit | 66 MHz | 528 MB/s | 4 to 5 |
| CompactPCI Serial (CPCI-S.0) | Serial SerDes | PCIe / Ethernet | Multiple GB/s per slot | 9 (1 system + 8 peripheral) |
At 66 MHz the higher loading reduces the usable slot count because faster edges tighten the signal-integrity budget on the shared parallel backplane, so designers trade slot count against clock speed. Note that 528 MB/s is an aggregate burst figure shared across the segment, not a per-slot guarantee.
Frequently Asked Questions
What is CompactPCI?
CompactPCI (cPCI) is a rugged industrial bus standard defined by PICMG 2.0 that maps the PCI electrical protocol onto a 3U or 6U Eurocard card cage. Cards plug vertically into a passive backplane through a gas-tight 2mm hard-metric (IEC 61076-4-101) connector, which tolerates shock, vibration, and thermal cycling far better than the edge-card connectors used in desktop PCI. A single bus segment supports up to 8 cards, one acting as the system controller and the rest as peripherals. In RF systems, cPCI chassis commonly host digital receivers, signal processors, and timing cards behind an RF front end.
How does CompactPCI differ from desktop PCI?
CompactPCI uses the same 33 or 66 MHz PCI bus protocol and signaling as desktop PCI, so software and silicon are largely reusable, but the physical and mechanical implementation is different. Desktop PCI uses horizontal cards with gold-finger edge connectors and supports about 4 loads per bus. CompactPCI uses vertical Eurocards retained by ejector handles, a 2mm hard-metric pin-and-socket connector with up to 220 contacts on 6U boards, and supports 8 cards per segment through more careful backplane impedance control. Front-panel I/O and rear-transition modules replace the rear-bracket connectors of desktop cards. The result is a serviceable, hot-swap-capable platform rated for harsh environments.
Is CompactPCI still used for RF and signal-processing systems?
Yes, CompactPCI remains in active use, especially in long-lifecycle defense, aerospace, and industrial programs that were fielded with 32 or 64-bit parallel-bus backplanes. For new high-bandwidth RF designs, switched-serial fabrics such as VPX (VITA 46) and CompactPCI Serial (PICMG CPCI-S.0) have largely replaced the legacy parallel bus because PCI Express, Ethernet, and SerDes links offer far higher throughput per slot. Many integrators still choose classic CompactPCI when the data rates are modest, the COTS ecosystem is mature, and backward compatibility with existing cards matters more than raw bandwidth.