Compact Thermal Model
Understanding Compact Thermal Model
Every RF and microwave device that dissipates power, whether a GaN power amplifier, a MMIC, or a millimeter-wave driver, heats up. The figure that matters most for reliability is the junction temperature, because device lifetime falls roughly exponentially as the junction gets hotter. The difficulty is that predicting that temperature accurately requires solving the heat equation across the chip, the attach layer, the package, and the heat sink, a task that takes minutes to hours in a finite-element solver. A compact thermal model condenses all of that physics into a handful of resistors and capacitors that a circuit simulator can evaluate almost instantly, while still reproducing the temperature at the points an engineer cares about.
The core idea is the well established analogy between heat flow and electrical current. Dissipated power plays the role of current, temperature difference plays the role of voltage, thermal resistance behaves like electrical resistance, and thermal capacitance behaves like electrical capacitance. Once heat transfer is cast in these terms, the whole toolkit of circuit analysis becomes available. A static power dissipation drives a steady temperature rise through the chain of thermal resistances, while the thermal capacitances govern how quickly the device reaches that steady state when power switches on or off.
Cauer and Foster Network Topologies
Two RC topologies dominate compact thermal modeling. A Cauer network is a ladder in which each resistor and capacitor pair maps to a physical layer of the device stack, so the internal node temperatures correspond to real interfaces such as the die surface, the attach, and the case. This makes the Cauer form physically meaningful and easy to partition by material. A Foster network, by contrast, is a series of parallel RC stages whose values are curve-fitted to a measured or simulated thermal transient. The Foster form reproduces the terminal junction-to-ambient response very accurately, but its internal nodes carry no physical meaning, so it cannot report interface temperatures. Designers often extract a Foster model from a measured cooling curve, then convert it to an equivalent Cauer ladder when physical node temperatures are needed.
Steady-State and Transient Behavior
In steady state the capacitors are fully charged and carry no heat flow, so the junction temperature is set entirely by the sum of thermal resistances between junction and ambient multiplied by the dissipated power. In the transient regime the capacitances dominate the early response: a short power pulse heats only the small thermal mass closest to the junction, while a long pulse eventually involves the package and heat sink. This time dependence is captured by the thermal impedance, often plotted as a curve of junction-to-case impedance versus pulse width. Pulsed and duty-cycled RF amplifiers depend heavily on this transient data, because their peak junction temperature can sit far below the value a steady-state calculation would predict.
Extraction and Validation
A compact model is only as good as the data behind it. Engineers extract the RC values either from a calibrated three-dimensional finite-element model or from measured thermal transients using a structure function, which is a mathematical transform of the cooling curve that reveals the resistance and capacitance of each physical layer. The model is then validated against an independent operating point. A trustworthy compact thermal model should track the full simulation or measurement within roughly five to ten percent across the intended power and pulse-width range, which is usually adequate for reliability budgeting and electrothermal co-simulation.
Key Equations
TJ = TA + PD × (RθJC + RθCA)
Transient form (thermal impedance):
TJ(t) = TA + PD × ZθJA(t)
Single RC stage time constant:
τ = Rθ × Cθ
Where TJ = junction temperature (°C), TA = ambient temperature (°C), PD = dissipated power (W), RθJC = junction-to-case thermal resistance (°C/W), RθCA = case-to-ambient thermal resistance (°C/W), ZθJA(t) = time-dependent junction-to-ambient thermal impedance (°C/W), Cθ = thermal capacitance (J/°C), and τ = stage thermal time constant (s). Example: PD = 8 W with RθJC = 2.5 and RθCA = 3.0 °C/W at TA = 25 °C gives TJ ≈ 69 °C.
Cauer vs. Foster Comparison
| Attribute | Cauer Network | Foster Network |
|---|---|---|
| Node meaning | Physical layer interfaces | Mathematical, non-physical |
| Internal temperatures | Available | Not available |
| Typical extraction | Layer geometry or FEM | Curve-fit to transient data |
| Best use | Interface temps, layered stacks | Junction-to-ambient response |
| Convertible to | Foster | Cauer |
Why Compact Models Matter for RF Systems
At millimeter-wave frequencies the heat dissipated in a small active area produces very high local power densities, so accurate temperature prediction is central to both performance and lifetime. A compact thermal model lets a designer co-simulate gain compression, bias drift, and self-heating together, run mission-profile temperature histories across thousands of operating states, and feed the result into a reliability model without ever rerunning a slow physical solver. That combination of speed and adequate accuracy is what makes the compact thermal model a standard deliverable alongside the electrical model for modern RF power devices.
Frequently Asked Questions
What is a compact thermal model?
A compact thermal model is a small network of thermal resistances and capacitances that represents how heat flows from a device junction to the ambient, letting engineers predict junction temperature and transient warm-up without solving the full three-dimensional heat equation. It is the fast, repeatable bridge between detailed physical simulation and bench-level temperature prediction for RF and microwave devices.
What is the difference between a Cauer and a Foster thermal network?
A Cauer network is a ladder of resistors and capacitors whose nodes correspond to physical material layers, so internal node temperatures such as the die surface and case are meaningful. A Foster network is a series of parallel RC stages curve-fitted to measured data; it reproduces the terminal junction-to-ambient response accurately but its internal nodes have no physical meaning. Engineers often extract a Foster model from a cooling curve, then convert it to a Cauer ladder when interface temperatures are needed.
Why use a compact thermal model instead of a full 3D simulation?
A compact thermal model runs in microseconds inside a circuit or system simulator, so it can be co-simulated with electrical behavior over millions of cycles and across full mission profiles. A full three-dimensional finite-element simulation is more accurate for a single static case but is far too slow for transient, duty-cycled, or closed-loop electrothermal analysis. A well-extracted compact model typically tracks the full simulation within five to ten percent across its intended power and pulse-width range.