Compact Model (Fab)
Understanding Compact Model (Fab)
A compact model bridges the gap between the physical world of the wafer and the abstract world of circuit simulation. When a foundry releases a process, designers cannot simulate every dopant atom or mesh the full three-dimensional device structure for each transistor in a circuit; that level of TCAD physics is far too slow for a multi-stage amplifier or a mixer. Instead, the foundry distills the device physics into a closed-form set of equations, the compact model, that returns drain current, gate charge, and the full set of small-signal parameters for any bias point, frequency, and temperature within the validated range. The word "compact" signals that the model is computationally light enough to evaluate millions of times during a single harmonic-balance or transient run.
Why Foundry Models Are Different
The defining feature of a fab compact model is that its parameters are not guessed; they are extracted from measured silicon or III-V wafers. The foundry fabricates a suite of test transistors at different gate widths and lengths, sweeps them on a probe station, captures DC current-voltage curves, capacitance-voltage data, and S-parameters across frequency, then fits the model equations to that data. The result is a parameter set that reproduces the real process, including the corner files that bracket the slow, typical, and fast process variations a wafer lot can exhibit. This is what separates a delivered PDK model from the idealized equations in a textbook: it encodes the actual behavior an RF Essentials customer will receive from that line.
What the Model Predicts
A complete RF compact model is more than a DC current equation. It must be charge-conserving so that the capacitances it implies are consistent with its currents, and it must remain continuous and differentiable so the simulator's Newton iteration converges. For high-frequency work the model also includes a non-linear large-signal description used for power, gain compression, and intermodulation prediction, plus an embedded thermal node so self-heating raises channel temperature and reduces current under drive. Designers extract a small-signal equivalent circuit from the model at each bias to read off transconductance, output conductance, and the cutoff and maximum-oscillation frequencies.
- DC behavior: drain current versus gate and drain voltage, including subthreshold and saturation regions
- Charge and capacitance: gate-source and gate-drain capacitances that set the device's frequency response
- Small-signal parameters: transconductance gm, output conductance gds, and the resulting fT and fmax
- Large-signal effects: gain compression, harmonic generation, and intermodulation for power applications
- Self-heating and noise: a thermal sub-network and a noise model for low-noise amplifier design
Common Model Families
Different device technologies use different industry-standard model formulations. Silicon CMOS overwhelmingly uses BSIM, with BSIM-CMG covering FinFET and gate-all-around nodes. Gallium arsenide and gallium nitride high electron mobility transistors are typically described by the ASM-HEMT, Angelov (also called the Chalmers model), or the legacy EEHEMT formulation. Silicon-germanium and III-V heterojunction bipolar transistors lean on HICUM or Mextram. The choice is dictated by what the foundry validates and ships, because a model is only as accurate as the parameters extracted for that specific process.
Key Small-Signal Relationships
gm = ∂ID / ∂VGS (at fixed VDS)
Cutoff frequency (current gain = 1):
fT = gm / [2π(Cgs + Cgd)]
Where:
ID = drain current (A)
VGS = gate-to-source voltage (V)
VDS = drain-to-source voltage (V)
gm = transconductance (S, siemens)
Cgs = gate-source capacitance (F)
Cgd = gate-drain capacitance (F)
fT = current-gain cutoff frequency (Hz)
These relationships are exactly what the compact model returns when a designer asks the simulator for a small-signal operating point. Higher transconductance and lower parasitic capacitance push fT upward, which is the figure of merit a millimeter-wave designer watches most closely.
Model Validation Ranges
| Parameter | What It Captures | Typical Validated Range | Design Impact |
|---|---|---|---|
| Bias (VDS) | Drain voltage sweep | 0 V to rated, often 0 to 6 V (GaAs), 0 to 28 V (GaN) | Out-of-range bias gives unreliable ID |
| Frequency | S-parameter fit span | DC to 2x to 3x fT | Sets valid simulation bandwidth |
| Temperature | Thermal scaling | -40 °C to +125 °C typical | Affects current and gain at extremes |
| Geometry | Gate width / finger count | Discrete validated cell sizes | Interpolation outside cells adds error |
| Process corners | Lot-to-lot variation | Slow / typical / fast files | Used for yield and margin analysis |
Designers who push a model outside these validated ranges, for example extrapolating to a frequency well beyond the S-parameter fit span, should treat the results with caution and confirm critical specifications on measured hardware. Pairing model-based simulation with on-wafer or fixture measurement is standard practice in any rigorous RF development flow, and it is how RF Essentials confirms that simulated and delivered performance agree.
Frequently Asked Questions
What is compact model fab?
A fab compact model is a foundry-supplied set of physics-based equations that predicts a device's terminal currents, charges, and small-signal behavior from its geometry and process parameters. It is distributed inside a Process Design Kit so circuit designers can simulate RF and microwave circuits in a SPICE-class simulator before committing a mask set. Each model's parameters are extracted by the foundry from on-wafer measurements of real test transistors.
How is a fab compact model different from a Process Design Kit?
A compact model is the mathematical core that describes one device type, such as a GaAs pHEMT or a CMOS transistor. A Process Design Kit is the complete package the foundry ships, which bundles the compact models together with layout cells, design rules, parasitic extraction decks, and process corner files. The compact model answers how a single device behaves, while the PDK supplies everything else needed to design a manufacturable circuit.
Which compact models are common for RF and microwave transistors?
For silicon MOSFETs the industry standard is BSIM, with BSIM-CMG used for FinFET nodes. For III-V high electron mobility transistors common choices include the ASM-HEMT, Angelov (Chalmers) and EEHEMT models, while bipolar and HBT devices often use HICUM or Mextram. RF Essentials selects the model that the device foundry validates and ships, since accuracy depends on parameters extracted from that specific process.