COIN Technology
Understanding COIN Technology
The fundamental reliability challenge in RF packaging is the CTE mismatch between the PCB and the components soldered to it. Standard FR-4 has a CTE of 14 to 17 ppm/°C in the x-y plane, while ceramic chip carriers (alumina, LTCC, AlN) range from 4.5 to 7 ppm/°C. During thermal cycling from -55 to +125°C (per MIL-STD-883), the differential expansion creates shear strain in solder joints proportional to the CTE mismatch, the temperature swing, and the distance from the neutral point. For a 25 mm ceramic package on FR-4, the corner joint strain can reach 1.5% per cycle, causing fatigue failure in as few as 200 cycles.
COIN substrates solve this by using invar (Fe-36Ni), an alloy with a CTE of only 1.2 ppm/°C, as the structural core. Copper cladding on both faces provides electrical conductivity and thermal spreading. The composite CTE is determined by the copper-to-invar thickness ratio through a rule-of-mixtures calculation. A 20/60/20 layup (20% copper per side, 60% invar core) yields about 5.5 ppm/°C, closely matching alumina. This reduces corner joint strain to 0.15%, extending thermal cycle life from 200 to over 2,000 cycles. The copper layers also serve as ground planes and power distribution, while signal traces route on dielectric layers bonded above the COIN core.
CTE and Solder Joint Life
αcomposite = (αCuECutCu + αInvEInvtInv) / (ECutCu + EInvtInv)
Solder Joint Shear Strain:
γ = Δα × ΔT × L / h
Coffin-Manson Fatigue Life:
Nf = C × γ-n
Where α = CTE (ppm/°C), E = elastic modulus, t = layer thickness, Δα = CTE mismatch, ΔT = temperature swing (°C), L = distance from neutral point (mm), h = solder joint height (mm), C and n are material constants (n ≈ 2 for SnPb). Halving Δα quadruples fatigue life.
CTE-Matched Substrate Comparison
| Substrate | CTE (ppm/°C) | Thermal Cond. (W/mK) | Density (g/cm³) | Best Use |
|---|---|---|---|---|
| FR-4 | 14 to 17 | 0.3 | 1.9 | Commercial, low cost |
| COIN (20/60/20) | 5.5 | 125 | 8.0 | Ceramic carrier matching |
| COIN (30/40/30) | 8.0 | 165 | 7.5 | LTCC/alumina matching |
| CuMo (15/70/15) | 6.0 | 180 | 9.5 | High-power GaN |
| AlSiC | 7.0 | 180 to 200 | 3.0 | Lightweight aerospace |
Frequently Asked Questions
Why is CTE matching important in RF assemblies?
When a ceramic chip carrier (CTE 6 to 7 ppm/°C) is soldered to FR-4 (CTE 14 to 17 ppm/°C), the 7 to 11 ppm/°C mismatch creates shear stress during thermal cycling from -55 to +125°C. This causes solder fatigue cracking in as few as 200 cycles. COIN substrates reduce mismatch to 1 to 2 ppm/°C, extending joint life by 5 to 10 times. This is critical for phased-array modules, satellite transponders, and avionics where field replacement is impractical.
How is a COIN substrate constructed?
Copper foil is bonded to both sides of an invar (Fe-36Ni) core sheet using solid-state diffusion bonding at 800 to 900°C. The copper-to-invar ratio controls the composite CTE: 20/60/20 yields about 5.5 ppm/°C, while 30/40/30 gives approximately 8 ppm/°C. The bonded sheet is then processed as a standard PCB core with drilling, plating, and etching. Total thickness ranges from 0.5 to 3.0 mm.
What are the RF performance trade-offs of COIN substrates?
COIN provides much higher thermal conductivity than FR-4 (120 to 170 vs. 0.3 W/mK), improving heat spreading under power devices. However, the ferromagnetic invar core can increase insertion loss at microwave frequencies through eddy current and hysteresis effects. Signal traces are confined to outer copper layers or separate dielectric layers. The higher density (8.0 vs. 1.9 g/cm³) increases board weight, a consideration for satellite and airborne platforms.