Why is CTE matching important in RF assemblies?

When two bonded materials have different CTEs, a temperature change creates differential strain at their interface. For a GaAs die (CTE 5.7 ppm/C) soldered to an FR-4 PCB (CTE 14 ppm/C), a 100 degree C temperature swing creates differential strain of (14-5.7) x 100 = 830 ppm, or 0.083%. For a 5 mm die, this corresponds to 0.42 micrometers of differential displacement at each edge, concentrated in the thin solder layer (50 to 100 micrometers). This shear strain accumulates with each thermal cycle (power cycling, environmental temperature changes), causing fatigue crack initiation and propagation in the solder. After 500 to 2,000 cycles (depending on temperature range and solder composition), the cracks can cause electrical open circuits. CTE-matched substrates (alumina at 6.5 ppm/C or AlN at 4.5 ppm/C for GaAs die, or CuMo composite at 6 to 8 ppm/C) reduce differential strain by 80 to 95%, extending solder joint life by 5 to 20 times. This is why military and space RF modules use ceramic substrates despite their higher cost.

How does CTE affect PCB via reliability?

The z-axis CTE of FR-4 is 60 to 70 ppm/C below the glass transition temperature (Tg, typically 130 to 180 degrees C) and 250 to 300 ppm/C above Tg, while the copper barrel plating in vias has CTE of 17 ppm/C. During soldering (peak temperature 245 to 260 degrees C), the z-axis expansion of FR-4 above Tg is approximately 5 to 8 times that of copper, creating enormous tensile stress in the via barrel. This can cause barrel cracking during assembly or early field life. The problem is worst for thick boards (more than 2 mm), small vias (less than 0.3 mm diameter), and high aspect ratio vias (more than 8:1). Solutions include using high-Tg laminates (Tg above 170 degrees C with low CTE z-axis filler materials), filled vias (epoxy fill reduces barrel stress), and via-in-pad designs with planarized fill. For RF applications, via reliability is critical because ground vias in microstrip-to-stripline transitions and decoupling vias must maintain low-impedance connections throughout the product life to avoid resonances and signal integrity degradation.

CTE is measured using thermomechanical analysis (TMA) where a probe tracks the length change of a sample as temperature is ramped at a controlled rate (typically 5 to 10 degrees C per minute). The instantaneous CTE at temperature T is alpha(T) = (1/L0) * dL/dT, and the average CTE over a range T1 to T2 is alpha_avg = (L(T2) - L(T1)) / (L0 * (T2 - T1)). Datasheets usually report the average CTE from 25 to 300 degrees C or from -55 to +125 degrees C (military range). For anisotropic materials like FR-4 laminates, CTE is measured separately in x, y (in-plane, constrained by glass fibers) and z (through-thickness, dominated by resin). The glass transition temperature creates a discontinuity in the CTE curve: below Tg, z-axis CTE is 60 to 70 ppm/C; above Tg, it jumps to 250 to 300 ppm/C. Low-CTE specialty laminates (Rogers RO4000 series, Arlon CLTE) use ceramic or glass fillers to reduce z-axis CTE to 30 to 50 ppm/C, improving via reliability for high-reliability RF applications.

Materials & Substrates

Coefficient Of Thermal Expansion

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CTE measures material expansion per degree C (ppm/°C). Critical for RF reliability: CTE mismatch >5 ppm/°C between bonded materials causes solder joint fatigue. Key values: Si 2.6, GaAs 5.7, alumina 6.5, AlN 4.5, FR-4 14 to 17 (xy) / 60 to 70 (z), Cu 17, SAC305 solder 22. CTE-matched ceramic substrates extend joint life 5 to 20x vs FR-4 for die attach. Z-axis CTE above T_g jumps to 250 to 300 ppm/°C, stressing vias.

Category: Materials & Substrates

FR-4 xy: 14 to 17 ppm/°C

Alumina: 6.5 ppm/°C

Understanding CTE in RF Engineering

Every material in an RF assembly expands when heated and contracts when cooled. When materials with different expansion rates are bonded together (die to substrate, component to PCB, substrate to heatsink), temperature changes create mechanical stress at the interfaces. This stress is proportional to the CTE difference, the temperature excursion, and the lateral dimensions of the bond. In consumer electronics with modest temperature ranges (0 to +70°C), standard FR-4 substrates and SAC solder survive thousands of thermal cycles despite significant CTE mismatches. In military, space, and automotive RF applications with extreme temperature ranges (-55 to +125°C or wider), CTE matching becomes a critical design parameter that dictates material selection, assembly processes, and expected field life.

The z-axis CTE of FR-4 deserves special attention in RF design. The in-plane (xy) CTE is constrained by the glass fiber reinforcement to 14 to 17 ppm/°C, reasonably close to copper's 17 ppm/°C. But the through-thickness (z) direction is dominated by the epoxy resin, with CTE of 60 to 70 ppm/°C below T_g and 250 to 300 ppm/°C above T_g. This creates enormous stress on plated through-hole vias during soldering (peak 250°C, well above T_g). For RF circuits with dense via fields (ground planes, decoupling), via cracking from z-axis CTE is a primary failure mechanism.

CTE Stress Equations

Differential Strain:
ε = (α₁ - α₂) × ΔT

Solder Joint Shear Strain:
γ = ε × L_die / (2 × h_solder)

Via Barrel Stress:
σ ≈ E_Cu × (α_z,FR4 - α_Cu) × ΔT × t_board / d_via

Where α = CTE (ppm/°C), ΔT = temperature swing, L_die = die half-length, h_solder = solder thickness. GaAs on FR-4, ΔT=100°C, 5mm die, 75μm solder: γ = 2.8% shear strain per cycle.

RF Material CTE Values

Material	CTE (ppm/°C)	κ (W/mK)	ε_r	RF Application
Silicon	2.6	148	11.7	CMOS RFIC
GaAs	5.7	46	12.9	MMIC
Alumina (Al₂O₃)	6.5	25	9.8	Hybrid modules
AlN	4.5	170	8.9	High-power PA
FR-4 (xy/z)	14 to 17 / 60 to 70	0.3	4.2	Commercial PCB

Common Questions

Frequently Asked Questions

Why is CTE matching important?

GaAs (5.7) on FR-4 (14): ΔCTE = 8.3 ppm/°C. At ΔT=100°C, 5mm die: 0.42 μm edge displacement, 2.8% solder shear strain per cycle. Fatigue failure in 500 to 2,000 cycles. CTE-matched ceramic (alumina 6.5 or AlN 4.5): strain reduced 80 to 95%, life extended 5 to 20x. Essential for military and space RF.

How does CTE affect via reliability?

FR-4 z-axis: 60 to 70 ppm/°C below T_g, 250 to 300 above T_g. Cu barrel: 17 ppm/°C. During reflow (250°C), 5 to 8x differential expansion. Worst for thick boards (>2 mm), small vias (<0.3 mm), high aspect ratio. Solutions: high-T_g laminates, filled vias, low-CTE fillers (Rogers, Arlon CLTE: 30 to 50 ppm/°C z).

How is CTE measured?

TMA: probe tracks length vs temperature at 5 to 10°C/min. Instantaneous α(T) = (1/L₀)dL/dT. Average over range. Anisotropic materials: separate xy and z measurements. T_g creates discontinuity in CTE curve. Datasheets report 25 to 300°C or -55 to +125°C average.

Related Terms

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