Coherent Receiver
Understanding Coherent Receiver
The coherent receiver is the critical enabling component for modern high-capacity optical networks. Unlike direct-detection receivers that measure only optical intensity (losing phase and polarization), the coherent receiver preserves all four quadratures of the optical field by interfering the signal with a strong LO reference. The intradyne approach uses a free-running LO laser with a frequency offset of up to several GHz from the signal carrier; the DSP corrects for this offset digitally, eliminating the need for an optical phase-locked loop. This greatly simplifies the receiver hardware while enabling flexible wavelength tuning.
The signal path begins with a polarization beam splitter separating the incoming fiber signal into X and Y polarization components. Each component enters a 90-degree optical hybrid along with the corresponding LO polarization. The hybrid produces four outputs per polarization: signal+LO, signal-LO, signal+jLO, and signal-jLO. Balanced photodetector pairs subtract complementary outputs to produce the I and Q photocurrents. Transimpedance amplifiers convert photocurrents to voltage with linear gain of 2 to 5 kΩ, and the ADCs digitize at 64 to 128 Gsamples/s. The four digitized streams feed the coherent DSP ASIC for equalization, carrier recovery, and demodulation.
Receiver Sensitivity
SNR = ηPs / (hνRs)
Balanced Detector Photocurrent:
iout = 2R × √(PsPLO) × cos(Δφ)
Receiver Sensitivity (at BER = 10-3):
Ps,min ≈ 20 hνRs / η (for DP-QPSK)
Where η = quantum efficiency (0.7 to 0.9), Ps = signal power, hν = photon energy (0.128 aJ at 1550 nm), Rs = symbol rate, R = responsivity (A/W), PLO = LO power, Δφ = phase difference. At 32 GBd DP-QPSK: Ps,min ≈ -46 dBm.
Coherent Receiver Architecture Comparison
| Parameter | Discrete ICR | Silicon Photonics ICR | InP Monolithic ICR | Design Impact |
|---|---|---|---|---|
| Integration | Hybrid (lens-coupled) | Wafer-scale, CMOS fab | Monolithic epitaxy | Cost at volume |
| Bandwidth | 40 to 45 GHz | 50 to 70 GHz | 50 to 65 GHz | Symbol rate limit |
| Responsivity | 0.6 to 0.8 A/W | 0.5 to 0.7 A/W (Ge PDs) | 0.7 to 0.9 A/W | Sensitivity |
| CMRR | 20 to 25 dB | 25 to 35 dB | 20 to 30 dB | RIN suppression |
| Size | 20 × 10 mm | 4 × 6 mm | 5 × 7 mm | Module form factor |
Frequently Asked Questions
What are the key components of a coherent optical receiver?
A coherent receiver contains a polarization beam splitter, a free-running LO laser (linewidth below 100 kHz), two 90-degree optical hybrids for I/Q mixing per polarization, four balanced photodetector pairs with 40 to 70 GHz bandwidth, and four TIAs with linear response. Modern ICRs integrate all optical components onto a single InP or silicon photonics chip measuring 4 by 6 mm, reducing assembly cost and improving phase and amplitude balance.
Why is balanced detection important in coherent receivers?
Balanced detection subtracts photocurrents from matched photodiode pairs, canceling the DC component and LO relative intensity noise. Since the LO power is 30 to 40 dB stronger than the received signal, RIN would dominate without cancellation. The subtraction also eliminates signal-signal beat noise. The result is shot-noise-limited operation within 1 to 3 dB of the theoretical sensitivity minimum for any given modulation format.
What bandwidth and sample rate does a modern coherent receiver need?
For 400G DP-16QAM at 64 GBd, each of the four electrical lanes needs 35 to 45 GHz analog bandwidth and ADC sampling at 64 to 128 Gsamples/s at 8 bits. Total receiver throughput reaches 2 to 4 Tsamples/s across all lanes. For 800G at 130 GBd, bandwidth extends to 70 GHz with interleaved ADCs at 256 Gsamples/s. The coherent DSP processes all lanes simultaneously in 5 nm CMOS consuming 15 to 25 W.