What is the recommended architecture for a direction-finding receiver that needs phase-coherent channels?

The recommended architecture for a direction-finding (DF) receiver that needs phase-coherent channels ensures that all receiver channels maintain a known and stable phase relationship, which is essential for accurately measuring the angle of arrival of incoming signals using phase interferometry. The architecture must address: common local oscillator (LO) distribution (all receiver channels must share the same LO signal to ensure that any LO phase noise or drift affects all channels equally; the LO is generated by a single synthesizer and distributed to all channels through a power divider network; the distribution network must maintain equal phase length to all channels (phase-matched within ±1-5 degrees at the operating frequency)), matched receiver channels (each receiver channel (antenna element to ADC) must have closely matched gain, phase, and group delay; amplitude matching: ±0.5 dB between channels (ensures accurate amplitude-comparison DF); phase matching: ±1-5 degrees between channels (the DF accuracy depends directly on the phase matching accuracy); group delay matching: ±1-5 ns between channels (for wideband signals, group delay mismatch causes frequency-dependent phase errors)), calibration (even with careful matching: residual phase and amplitude differences exist between channels due to component tolerances, cable length differences, and temperature drift; these are removed by calibration: inject a common calibration signal into all channels simultaneously (through directional couplers at the antenna port); measure the phase and amplitude difference between each channel pair; store the calibration data and apply corrections to the DF measurements; recalibrate periodically or continuously to track temperature drift), and simultaneous sampling (all ADCs must sample at the same instant (or with a known, compensated time offset); a common sampling clock distributed to all ADCs with matched-length clock lines ensures simultaneous sampling; jitter in the sampling clock creates phase noise that degrades the DF accuracy (the phase error from clock jitter: delta_phi = 2 x pi x f_signal x delta_t_jitter)).