Quantum Computing and Quantum RF Qubit Control and Readout Informational

What is the required phase noise of the microwave source for coherent qubit control?

Q: Is phase noise more important than amplitude noise?

For single-qubit gates: phase noise and amplitude noise contribute comparably to gate infidelity. However, phase noise is harder to control because: (1) Phase noise from free-running oscillators has a 1/f^2 (or worse) spectrum, concentrating noise at low frequencies where it contributes most to dephasing. (2) Amplitude noise can be reduced by operating in the linear regime (far from compression), while phase noise is intrinsic to the oscillator. (3) Common-mode amplitude fluctuations can be partially rejected by using auto-leveling circuits. In practice, phase noise is usually the limiting source specification for qubit control.

Q: Does the readout LO have the same phase noise requirement?

The readout LO phase noise requirement is actually tighter in some respects. For dispersive readout, the phase noise of the readout LO adds directly to the measurement noise: sigma_phi_readout appears as noise in the IQ demodulation, reducing SNR. For a readout integration time of 1 μs: the relevant noise bandwidth is 1 MHz, and the integrated phase noise from 1 Hz to 1 MHz must be small. Typical requirement: <-115 dBc/Hz at 100 kHz for 99.9% readout fidelity. Most high-quality signal generators meet this easily. For multi-qubit systems, using the same LO for readout and demodulation (homodyne or digital downconversion) cancels common-mode phase noise, relaxing the absolute requirement.

Q: Can I use a PLL synthesizer for qubit control?

Yes, but with limitations. PLL synthesizers (ADF4351, LMX2594) have phase noise of -95 to -110 dBc/Hz at 10 kHz offset, which is 20-35 dB worse than high-end signal generators. This limits single-qubit gate fidelity to approximately 99.5-99.9% for uncompensated operations. Mitigation strategies: (1) Use echo-based gate sequences (X-Y-X or similar) that refocus slow phase noise, effectively filtering out noise below the echo rate. (2) Use a higher-quality VCXO or OCXO as the PLL reference to reduce close-in phase noise. (3) Share one PLL across multiple qubits and exploit correlations. PLL synthesizers are appropriate for systems where cost per channel ($20-100) is more important than per-gate fidelity, such as early development platforms and educational systems.

The microwave source used for qubit control must have sufficiently low phase noise to avoid introducing dephasing during gate operations. Phase noise from the source creates random fluctuations in the qubit drive phase, which translates to random rotation angle errors that accumulate as dephasing. The phase noise requirement is derived from the target gate fidelity: the integrated phase noise power from DC to the qubit linewidth (1/(pi×T2) ≈ 3-30 kHz for modern transmons) must be small compared to the gate error budget. For single-qubit gate fidelity of 99.99%: the phase error per gate must be < 0.01 radians. For a 20 ns gate, this requires that the integrated phase noise from f_offset = 1/(2×T_gate) = 25 MHz down to DC contribute < 0.01 rad^2 of phase variance. Practically, this translates to phase noise specification of: < -80 dBc/Hz at 10 Hz offset, < -100 dBc/Hz at 1 kHz offset, < -120 dBc/Hz at 100 kHz offset, and < -140 dBc/Hz at 10 MHz offset. High-quality commercial microwave signal generators meet these requirements: Keysight E8267D, Rohde & Schwarz SMW200A, and Holzworth HS9000 series. Lower-cost options (RFMD/Analog Devices PLL synthesizers) achieve -100 dBc/Hz at 10 kHz offset, marginal for high-fidelity gates. For systems with many qubits, sharing one LO across multiple qubits (via power splitters) ensures correlated phase noise that can be partially refocused using echo sequences, relaxing the per-source requirement.

Category: Quantum Computing and Quantum RF

Updated: April 2026

Product Tie-In: Microwave Sources, IQ Mixers, Amplifiers, Cryogenic Components

Phase Noise in Qubit Control

Phase noise is one of the key specifications distinguishing laboratory-grade from production-grade quantum control systems. Insufficient phase noise directly limits gate fidelity and cannot be corrected by post-processing or calibration.

Technical Considerations

The LO phase noise spectrum L(f) [dBc/Hz] describes the power spectral density of phase fluctuations at offset frequency f from the carrier. The total phase variance from the source is: sigma_phi^2 = 2 × integral(10^(L(f)/10) df) from f_low to f_high. The integration limits: f_low is determined by the measurement repetition rate or echo sequence rate (typically 1 kHz to 1 MHz), f_high is set by the gate bandwidth (1/(2*T_gate) ≈ 25 MHz for 20 ns gate). For a typical LO with L(f) = -120 dBc/Hz at 100 kHz: if the phase noise is flat from 1 kHz to 25 MHz: sigma_phi^2 = 2 × 10^-12 × 25 × 10^6 = 5 × 10^-5 rad^2, sigma_phi = 7 × 10^-3 rad. Gate infidelity from phase noise: 1-F ≈ sigma_phi^2 / 2 = 2.5 × 10^-5, corresponding to 99.997% fidelity. This is adequate for current systems but will become limiting for future gates targeting 99.999% fidelity.

Performance Analysis

High-end signal generators ($10,000-50,000): Keysight E8267D/N5183B: -130 dBc/Hz at 10 kHz, -150 dBc/Hz at 1 MHz. Rohde & Schwarz SMA100B: -132 dBc/Hz at 10 kHz, -152 dBc/Hz at 1 MHz. Holzworth HS9000: -135 dBc/Hz at 10 kHz, -150 dBc/Hz at 1 MHz. These provide negligible phase noise contribution to gate errors and are the standard for research systems. Mid-range synthesizers ($2,000-10,000): Windfreak SynthHD Pro: -110 dBc/Hz at 10 kHz. Valon 5009: -108 dBc/Hz at 10 kHz. Adequate for development and characterization but may limit gate fidelity to 99.9-99.95%. Integrated PLL synthesizers ($10-100, on a control board): ADF4351, MAX2871, LMX2594: -95 to -105 dBc/Hz at 10 kHz. Marginal to inadequate for high-fidelity gates. Used in some multi-qubit control systems where cost per channel is critical, with echo sequences to mitigate the phase noise impact.

Performance verification: confirm specifications against the application requirements before finalizing the design
Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades

Design Guidelines

For a 100-qubit system with 100 qubit drive frequencies: (1) Individual LO per qubit: 100 signal generators at $10,000 each = $1M. Phase noise is uncorrelated between qubits. (2) Shared LO with sideband modulation: 10-20 LOs, each driving 5-10 qubits via IQ mixers at different f_IF values. Phase noise from a shared LO is correlated across all qubits it drives; correlated phase errors can be partially refocused by simultaneous echo pulses on all sharing qubits. (3) Direct synthesis (Zurich SHFQC, Quantum Machines OPX+): the DAC generates the signal directly; phase noise is set by the DAC clock phase noise multiplied by the synthesis ratio. A 2 GSa/s DAC synthesizing a 100 MHz IF has phase noise equal to the clock reference phase noise at 2 GHz; the equivalent phase noise at 5 GHz (after upconversion) is degraded by 20×log(5000/2000) = 8 dB. Use a low-noise reference clock (10 MHz OCXO with -170 dBc/Hz floor) to achieve adequate performance.

Common Questions

Frequently Asked Questions

Is phase noise more important than amplitude noise?

For single-qubit gates: phase noise and amplitude noise contribute comparably to gate infidelity. However, phase noise is harder to control because: (1) Phase noise from free-running oscillators has a 1/f^2 (or worse) spectrum, concentrating noise at low frequencies where it contributes most to dephasing. (2) Amplitude noise can be reduced by operating in the linear regime (far from compression), while phase noise is intrinsic to the oscillator. (3) Common-mode amplitude fluctuations can be partially rejected by using auto-leveling circuits. In practice, phase noise is usually the limiting source specification for qubit control.

Does the readout LO have the same phase noise requirement?

The readout LO phase noise requirement is actually tighter in some respects. For dispersive readout, the phase noise of the readout LO adds directly to the measurement noise: sigma_phi_readout appears as noise in the IQ demodulation, reducing SNR. For a readout integration time of 1 μs: the relevant noise bandwidth is 1 MHz, and the integrated phase noise from 1 Hz to 1 MHz must be small. Typical requirement: <-115 dBc/Hz at 100 kHz for 99.9% readout fidelity. Most high-quality signal generators meet this easily. For multi-qubit systems, using the same LO for readout and demodulation (homodyne or digital downconversion) cancels common-mode phase noise, relaxing the absolute requirement.

Can I use a PLL synthesizer for qubit control?

Yes, but with limitations. PLL synthesizers (ADF4351, LMX2594) have phase noise of -95 to -110 dBc/Hz at 10 kHz offset, which is 20-35 dB worse than high-end signal generators. This limits single-qubit gate fidelity to approximately 99.5-99.9% for uncompensated operations. Mitigation strategies: (1) Use echo-based gate sequences (X-Y-X or similar) that refocus slow phase noise, effectively filtering out noise below the echo rate. (2) Use a higher-quality VCXO or OCXO as the PLL reference to reduce close-in phase noise. (3) Share one PLL across multiple qubits and exploit correlations. PLL synthesizers are appropriate for systems where cost per channel ($20-100) is more important than per-gate fidelity, such as early development platforms and educational systems.

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