What is the recommended sequence for applying gate and drain bias to a GaN amplifier?

The recommended sequence for applying gate and drain bias to a GaN amplifier is to apply the negative gate voltage first (before the drain voltage) and remove the drain voltage first (before the gate voltage) during power-down, following the sequence: gate-first-on, drain-second-on, drain-first-off, gate-second-off. This sequence is critical because: GaN HEMTs are depletion-mode devices (normally on: with zero gate voltage, the transistor conducts maximum current), applying the drain voltage without first pinching off the channel with a negative gate voltage causes the transistor to draw maximum drain current (I_dss, which can be several amperes), which may exceed the device's safe operating area (SOA), overheat the transistor, or damage it. The proper sequence is: power-on: set the gate voltage to the desired bias point (typically -2 to -3 V for a GaN HEMT, corresponding to 100-500 mA of quiescent current) BEFORE applying the drain voltage; the gate voltage establishes the quiescent current at zero drain voltage (no power dissipation); then ramp up the drain voltage (typically 28-50 V) slowly (over 1-10 ms); the transistor draws only the quiescent current because the operating point is already established. Power-off: reduce the drain voltage to 0 V first (removes the power dissipation), then release the gate voltage to 0 V (the transistor returns to its full-on state, but with no drain voltage there is no power dissipation). This sequence prevents the high-current, high-voltage condition that would occur if the drain voltage were applied to an unpinched device. The bias sequencing can be implemented with: a dedicated sequencing IC (such as Analog Devices ADM1166 or LTC2924), a microcontroller with timed GPIO outputs driving voltage regulators, or discrete RC delay circuits that ensure proper timing.