What is the recommended design review checklist for an RF circuit board before fabrication?
RF PCB Pre-Fabrication Review
A thorough design review before PCB fabrication prevents costly respins and schedule delays. RF boards are particularly sensitive to layout errors because electromagnetic effects (coupling, radiation, impedance discontinuities) are not always visible in schematic-level simulation.
Impedance and Transmission Line Checks
Critical items: (1) Verify the PCB stackup with the fabricator before design: layer count, dielectric material (Rogers 4003C/4350B for <20 GHz, Megtron 6/7 for digital+RF mixed, Isola Astra MT77 for mmWave), dielectric thickness, and copper weight. (2) Calculate transmission line widths for each signal layer using the actual stackup (not a generic rule of thumb). A 1-mil error in dielectric thickness changes microstrip impedance by ~3 ohms. (3) Check every transition: microstrip-to-GCPW, connector launch pad geometry, via transitions between layers. Each transition should be modeled in 3D EM simulation for frequencies above 6 GHz. (4) Verify that meander lines (for phase matching or delay) maintain consistent impedance around bends (use mitered or curved bends, not right angles). (5) Check that coupled-line structures (couplers, filters) have correct coupling gap for the stackup. (6) For differential pairs: verify spacing, length matching (<1% of wavelength at the highest harmonic), and maintain impedance through connectors and vias.
Grounding and Shielding
(1) Ground via fencing: place ground vias along both sides of every RF trace at spacing < lambda/20 at the highest operating frequency. At 10 GHz: lambda = 30 mm in air, ~15 mm on PCB; via spacing < 0.75 mm. (2) Check for return current path continuity: the ground plane under an RF trace must be uninterrupted. Any slot or gap in the ground forces the return current to detour, creating an inductance that disrupts impedance and radiates. (3) Verify shielding can footprints: solder pads for shield cans must be continuous (no gaps for trace routing), with ground vias at regular intervals along the perimeter (every 1-2 mm). (4) Check for ground plane copper fills: all unused copper should be filled and stitched to ground with vias to prevent resonant patches. (5) Verify that digital signals do not route under or adjacent to sensitive RF blocks (LNA input, VCO, reference oscillator).
Fabrication and Assembly Notes
(1) Include impedance control notes in the fab drawing: specify controlled impedance layers, target impedance ±10%, and the dielectric constant and thickness for each layer. (2) Mark RF-critical dimensions with tight tolerances (trace width ±0.5 mil for microstrip, gap ±0.5 mil for coupled lines). (3) Specify surface finish compatible with RF performance: ENIG (Electroless Nickel Immersion Gold) for wire bonding and consistent contact resistance, or OSP (Organic Solderability Preservative) for lower cost with acceptable RF performance. Avoid HASL (Hot Air Solder Leveling) for RF traces above 1 GHz due to surface roughness. (4) Include assembly notes for RF components: orientation markings for directional devices (filters, amplifiers, couplers), solder paste specifications for small RF components (Type 4 or 5 paste for 0201/01005), and reflow profile compatible with the RF laminate (some RF laminates have lower decomposition temperatures than standard FR-4). (5) Include test specifications: impedance TDR measurements on coupons, insertion loss of test traces, and functional RF test points.
Via Spacing: s < λ/(20·√εᵣ)
Decoupling Cap: C > 10/(2πfZ₀)
Ground Via Inductance: L ≈ 0.2nH per 10-mil via
Thermal Via Array: R_th ≈ R_via/N_vias
Frequently Asked Questions
How many review iterations are typical before RF PCB fabrication?
For a new RF design: 2-3 formal review iterations are standard. First review: schematic and component selection (before layout begins). Second review: layout review (after placement, before routing is complete). Third review: final review with completed routing, DRC clean, and all fab notes. Each review should involve at least one reviewer besides the designer (peer review catches errors the designer is blind to). For experienced teams doing incremental updates to existing designs: 1 review may suffice. Quick-turn prototype fabrication (3-5 day turn) often justifies a slightly less thorough review compared to production boards with 6-8 week lead times.
What are the most common RF PCB design mistakes?
The top 5 errors that cause board respins: (1) Ground plane discontinuity under an RF trace (slot from a signal route on an adjacent layer). (2) Incorrect transmission line width due to wrong stackup assumptions (designer used nominal dielectric thickness instead of the fabricator actual stackup). (3) Missing DC blocking capacitor on an RF path (causes DC offset that damages downstream components or biases amplifiers incorrectly). (4) Via transition not designed for the operating frequency (acceptable at 1 GHz but creates 3 dB loss at 10 GHz). (5) Connector footprint mismatch (the land pattern does not match the actual connector dimensions, causing impedance bump and poor soldering). All of these are catchable in a thorough design review.
Should I simulate the full PCB layout before fabrication?
For operating frequencies above 6 GHz: yes, simulate critical RF paths using 3D EM tools (Ansys HFSS, CST Studio, Keysight ADS Momentum). Focus on: connector launches, via transitions, filter and coupler structures, and any custom impedance matching networks. Simulation time is well spent: finding a 2 dB loss in a via transition in simulation costs 2 hours; finding it after fabrication costs 2 weeks and $5,000+ for a respin. For frequencies below 3 GHz: 3D simulation is typically unnecessary if standard RF layout practices are followed. 2D cross-section tools (for impedance) and circuit simulation (for matching networks) are sufficient.