System Integration and Packaging Module and Package Design Informational

What is a system in package approach for RF and how does it reduce size and cost?

Q: Who manufactures RF SiP modules?

Leading RF SiP module manufacturers include Qualcomm (RF360 joint venture with TDK), Skyworks Solutions, Qorvo, Broadcom (Avago), and Murata. These companies produce the front-end modules used in virtually all smartphones. The SiP packaging is performed by outsourced semiconductor assembly and test (OSAT) companies including ASE, Amkor, JCET, and STATS ChipPAC, or by the module companies' internal packaging facilities.

A System-in-Package (SiP) for RF is what the industry calls an advanced packaging approach that does integrate multiple semiconductor die (from potentially different fabrication processes), passive components, and interconnects into a single package to reduce the overall size and cost of a complete RF functional block. Unlike a traditional multi-chip module (MCM) that uses a ceramic substrate with wire bonds, SiP leverages advanced packaging technologies including embedded die, redistribution layers (RDL), through-mold vias (TMV), and fan-out wafer-level packaging (FOWLP) to achieve much higher integration density. An RF SiP might integrate a GaAs PA die, a silicon CMOS controller/DSP die, SAW/BAW filters, matching inductors and capacitors (either discrete or embedded in the RDL), and ESD protection, all within a single package measuring 5x5 mm or smaller. This approach can reduce size by 50-80% versus the equivalent discrete-component PCB assembly, reduce cost by eliminating separate PCB area, assembly steps, and interconnections, and improve RF performance by shortening signal paths and providing controlled-impedance interconnects with lower parasitics than board-level assembly. SiP is the dominant integration approach for smartphone RF front-end modules (produced in billions of units annually), enabling the complex multi-band, multi-mode operation required by modern cellular standards.

Category: System Integration and Packaging

Updated: April 2026

Product Tie-In: Packages, Substrates, Assembly Materials

System-in-Package Technology for RF Integration

SiP has revolutionized the RF module industry, particularly for high-volume consumer electronics. The complexity of modern wireless standards (4G/5G with 30+ frequency bands, each requiring dedicated PA, LNA, filter, and switch) makes board-level integration impractical, driving the industry toward SiP solutions.

SiP Technology Options

Laminate SiP: Multiple die mounted on a multi-layer organic substrate (similar to BGA). Wire bonds connect die to substrate. Moderate density, widely used for Wi-Fi and Bluetooth modules
Fan-Out Wafer-Level Packaging (FOWLP): Die embedded in a reconstituted wafer, with RDL layers providing interconnect. No substrate needed. Smallest package size, lowest profile. Used for high-end smartphone RF front-end modules
Embedded die SiP: Die are embedded within the laminate substrate (not on top). Provides shortest interconnects and best RF performance. More complex fabrication
3D SiP: Die stacked vertically with through-silicon vias (TSV) or through-mold vias (TMV). Maximum density but complex thermal management. Used for memory-over-logic stacking

RF SiP Design Challenges

Isolation between integrated PA and LNA (especially when both are active during CA or full-duplex operation), thermal management (PA die generates heat that affects adjacent temperature-sensitive filters), RDL design for controlled impedance (50-ohm lines in thin RDL layers), and known-good-die (KGD) testing (each die must be tested before integration to maintain package yield).

SiP Performance Parameters

SiP size reduction vs PCB: 50-80% area reduction typical
SiP cost advantage (high volume): 20-40% reduction vs discrete assembly
RDL impedance: Z0 = 60/sqrt(Er_eff) x ln(2h/w) for microstrip in RDL
Interconnect inductance: FOWLP bump ~ 0.05 nH vs wire bond ~ 0.5-1 nH
Package yield: Y_SiP = Y_die1 x Y_die2 x ... x Y_assembly

Common Questions

Frequently Asked Questions

How many die can be integrated in a single SiP?

Modern RF SiP modules integrate 2-8 die plus multiple passive components in a single package. Complex 5G front-end modules may integrate GaAs PA die, SOI switch die, BAW filter die, CMOS controller/PMIC die, and discrete matching components. The total die count is limited by package size, yield considerations (more die means lower package yield), and interconnect complexity.

What is the cost advantage of SiP versus discrete assembly?

At smartphone volumes (millions of units), SiP provides 20-40% total cost reduction versus discrete assembly on the main PCB. The savings come from: reduced PCB area (which is expensive in smartphones at $0.01-0.05/mm^2), fewer assembly steps, fewer SMT placement operations, and improved yield (fewer solder joints that can fail). At lower volumes (<100K units), the SiP advantage is smaller because the tooling and package development costs are significant.

Who manufactures RF SiP modules?

Leading RF SiP module manufacturers include Qualcomm (RF360 joint venture with TDK), Skyworks Solutions, Qorvo, Broadcom (Avago), and Murata. These companies produce the front-end modules used in virtually all smartphones. The SiP packaging is performed by outsourced semiconductor assembly and test (OSAT) companies including ASE, Amkor, JCET, and STATS ChipPAC, or by the module companies' internal packaging facilities.

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