How does crosstalk between microwave control lines limit the scalability of a quantum processor?
Quantum Processor Crosstalk
Crosstalk is fundamentally a microwave engineering challenge and is increasingly recognized as the bottleneck for scaling quantum processors to thousands of qubits.
Frequently Asked Questions
How is crosstalk measured in a quantum processor?
Crosstalk measurement protocol: (1) Randomized benchmarking: apply random gate sequences to qubit A while monitoring qubit B (which should remain idle). If qubit B shows errors correlated with the activity on qubit A: crosstalk is present. (2) AC Stark shift measurement: drive qubit A strongly and measure the frequency shift of qubit B. The shift is proportional to the power coupling from line A to qubit B. This gives a direct measurement of the crosstalk coefficient. (3) Simultaneous gate benchmarking: measure the error rate of a gate on qubit A when qubit B is simultaneously being driven vs when B is idle. The difference in error rate is attributed to crosstalk.
Can software correction fully compensate for crosstalk?
Partially. Crosstalk calibration: measure the N×N crosstalk matrix (the coupling coefficient from each line to each qubit). When applying a pulse to qubit A: simultaneously apply a compensating pulse (inverted and scaled by the crosstalk coefficient) to all neighboring lines. This cancels the crosstalk at the qubit. Limitations: (1) The calibration is time-consuming (scales as N²). (2) The crosstalk coefficients drift with temperature, frequency, and time (recalibration needed periodically). (3) Higher-order effects (crosstalk of the compensation pulses) create residual errors. (4) The DAC resolution limits the compensation accuracy (a 16-bit DAC can null to approximately -96 dBFS). In practice: software compensation can reduce crosstalk by 20-40 dB (from -40 dB to -60 to -80 dB). Combined with hardware isolation: total isolation > 80 dB is achievable.
What is the current state of quantum processor scaling?
As of 2025: IBM: 1,121 qubits (Condor processor, announced 2023). The control system uses dedicated lines per qubit with extensive crosstalk calibration. Google: 70+ qubits (Sycamore architecture). Focus on error correction with high-fidelity gates. Intel: 12 qubits on cryo-CMOS with integrated control (Horse Ridge controller). The bottleneck for scaling beyond ~1000 qubits is the wiring: each qubit requires 2-3 coaxial cables from room temperature to the mixing chamber. For 10,000 qubits: 20,000-30,000 cables are impractical (thermal load, physical space). Solutions: multiplexed control (fewer lines), cryogenic electronics (shorter lines), and photonic interconnects (optical fibers with much lower thermal conductivity than coax).