How do I set up boundary conditions for a waveguide port excitation in an EM simulator?
Waveguide Port Setup in EM Simulation
Waveguide ports are the interface between the simulated structure and the circuit-level description (S-parameters). Incorrect port setup is the most common source of simulation errors, especially for planar transmission lines where the port boundary and integration line significantly affect results.
Port Sizing
The port boundary must be large enough to contain the complete field pattern of the modes being solved, but small enough to avoid exciting spurious higher-order modes. Rules of thumb for common transmission line types: Rectangular waveguide: port matches the waveguide cross-section exactly; no sizing ambiguity. Coaxial: port includes the full dielectric between inner and outer conductors, bounded by the outer conductor wall. Microstrip: port width should extend at least 5× the trace width on each side (to capture fringing fields), and port height should be 8-10× the substrate thickness above the trace. If the port is too small, the mode fields are clipped, causing impedance errors (typically the computed impedance is higher than reality). If the port is too large for microstrip, it may excite the parallel-plate waveguide mode between the substrate and the port boundary, creating a spurious resonance. CPW (coplanar waveguide): port must contain both grounds and the signal trace, with lateral extent 3-5× the gap-plus-signal width.
Integration Line and Impedance Reference
For TEM and quasi-TEM modes (microstrip, stripline, CPW), the port impedance must be referenced to a voltage definition. The integration line is a line segment on the port face from the signal conductor to the reference ground, and the voltage is computed as the line integral of E-field along this path. In HFSS: draw the integration line from the center of the signal trace perpendicular to the ground plane. For CPW: draw from the signal conductor to one ground. The position and path of the integration line affects the computed impedance by 1-5 ohms for typical microstrip/CPW geometries. Best practice: use the same integration line definition consistently across all ports in a multi-port structure, and verify that the computed port impedance matches your transmission line design impedance (e.g., 50 ohms ± 1-2 ohms).
Common Port Mistakes
(1) Port placed inside a discontinuity: the port must be in a uniform section of transmission line where only the desired mode propagates. Placing a port at or near a bend, step, or junction causes the 2D mode solver to compute incorrect mode shapes. Add a short length (3-5× substrate height for microstrip) of uniform line between the discontinuity and the port. (2) Missing de-embedding: if the port is set back from the reference plane by a length of uniform line, failing to de-embed includes that line length in the S-parameters, adding phase delay and obscuring the actual discontinuity behavior. (3) Wrong number of modes: for a waveguide T-junction where TE10 and TE20 can couple, computing only 1 mode misses the higher-order coupling and produces incorrect S-parameters. (4) Floating ground: in multilayer PCB simulations, each port must reference the correct ground layer. A port referenced to the wrong ground layer produces nonsensical impedance values.
Port Impedance: Z = V / I = ∫E·dl / ∮H·dl
De-embed Phase: S_de = S_port × exp(j×2×β×L)
Microstrip Port Height: H_port ≥ 8-10 × h_substrate
Frequently Asked Questions
How many modes should I include at each port?
For a single-mode transmission line (coaxial, microstrip below first higher-order mode): 1 mode is sufficient. For rectangular waveguide at frequencies approaching the TE20 cutoff: include 2-3 modes. For overmoded waveguide or multi-mode structures: include all propagating modes plus 1-2 evanescent modes. For coupled-line structures (coupled microstrip, dual-mode filters): include at least 2 modes per port to capture even and odd mode behavior. Over-specifying modes increases computation time but does not cause errors. Under-specifying modes causes missing coupling paths and incorrect S-parameters.
How do I verify my port setup is correct?
Three checks: (1) Examine the port mode field pattern. It should match the expected mode shape (E-field concentrated between signal and ground for TEM, zero at walls and maximum at center for TE10). Distorted or asymmetric patterns indicate sizing or placement errors. (2) Check computed port impedance: it should be within 2-3% of the design impedance (e.g., 49-51 ohms for a 50-ohm line). (3) Simulate a uniform section of transmission line (no discontinuity) with two identical ports: S21 should be near 0 dB with linear phase slope, and S11 should be below -40 dB. Any deviation indicates port setup error or insufficient mesh resolution.
What is the difference between waveport and lumpedport in HFSS?
Wave ports excite a 2D mode solution at the boundary of the simulation domain and are used when the transmission line extends to the edge of the model (the port replaces the infinite transmission line). Lumped ports excite a uniform E-field between two conductors inside the simulation domain and are used for internal excitation (e.g., feeding an antenna with a discrete source, or exciting a via from one layer to another). Wave ports are more accurate for S-parameter extraction because they account for the actual mode field distribution. Lumped ports assume a uniform field, which is approximate for transmission lines but adequate for electrically small feed gaps ( < lambda/20).