How do I select the right prepreg for bonding layers in a multilayer RF PCB stackup?
Prepreg Selection for RF Stackups
The prepreg is the "invisible layer" that is often overlooked in RF stackup design but has a direct impact on stripline impedance, loss, and manufacturing repeatability.
- Performance verification: confirm specifications against the application requirements before finalizing the design
- Environmental factors: temperature range, humidity, and vibration affect long-term reliability and parameter drift
- Cost vs. performance: evaluate whether the application demands premium components or standard commercial grades
- Interface compatibility: verify impedance, connector type, and mechanical form factor match the system architecture
Frequently Asked Questions
How many prepreg plies do I need?
The number of plies is determined by the required dielectric thickness: 1 ply: achieves 3-4 mil pressed thickness (typical for thin dielectrics). 2 plies: 6-8 mil (common for standard RF stackups). 3 plies: 9-12 mil (for wider spacing). Using an odd number of plies (1 or 3): may result in asymmetric glass weave orientation (which can affect Dk uniformity). Using an even number (2 or 4): provides symmetric weave. Most RF designs use 1-2 plies. The fab house will recommend the number of plies based on your required dielectric thickness.
What about bonding films?
For PTFE-to-PTFE bonding: standard prepregs do not bond well to PTFE surfaces (PTFE is chemically inert). Bonding films: Rogers CuClad 6700 (FEP bond film) or Taconic FastRise 27 (low-loss bonding film). These films have low Dk (2.3-2.9) and Df (< 0.003), making them suitable for RF stackups. The bonding film thickness becomes part of the dielectric spacing and must be included in the impedance calculation.
Does prepreg affect via reliability?
Yes. The resin between layers forms the insulating barrier around the via barrel. If the resin has voids (from insufficient flow): the via-to-via isolation may be compromised. If the resin cracks during thermal cycling (brittle resin): the via barrels can lose their connection to the inner copper layers (barrel crack). For RF PCBs: use prepregs with: high resin flow (to fill around traces and vias without voids), matched CTE to the core (to minimize thermal stress on vias), and proven reliability (qualified per IPC-6012 Class 2 or Class 3).