Power, Linearity, and Distortion Compression and Intercept Points Informational

How do I determine the required IP3 for each stage in a receiver to meet a system linearity spec?

Determining the required IP3 for each stage in a receiver chain requires working backward from the system SFDR or linearity specification using the cascade IP3 formula: (1) System specification: start with the required SFDR (or IM3 specification for a given input level). From SFDR: IIP3_system = N_floor + (3/2) × SFDR. Example: SFDR = 70 dB and N_floor = -100 dBm: IIP3_system = -100 + 105 = +5 dBm. (2) Cascade IP3 formula (in linear power, not dB): 1/IIP3_total = 1/IIP3_1 + G1/IIP3_2 + G1×G2/IIP3_3 + ... Where G1, G2 = stage gains (linear, not dB), and IIP3_n = stage IIP3 (in mW, not dBm). Each succeeding term has all previous gains multiplied in. (3) Allocation strategy: the stage with the most gain before it contributes the most to the cascade IP3 degradation. Typically: the last IF amplifier (before the ADC) sees the highest signal levels and dominates the cascade IIP3. So: assign the most demanding IIP3 to the last active stage. Assign moderate IIP3 to intermediate stages. The first stage (LNA) can have relatively low IIP3 (because its gain has not yet amplified the signal, but its NF is critical). (4) Example: 3-stage receiver: LNA (gain = 20 dB, IIP3 = 0 dBm) → filter (loss = 3 dB) → mixer (gain = -6 dB, IIP3 = +15 dBm). Cascade: 1/IIP3_total = 1/1mW + 100×0.5/(31.6mW) = 1 + 1.58 = 2.58. IIP3_total = 1/2.58 mW = 0.387 mW = -4.1 dBm. The cascade IIP3 (-4.1 dBm) is worse than any individual stage. The mixer term dominates because the LNA gain (20 dB = 100×) multiplies its contribution.

Category: Power, Linearity, and Distortion

Updated: April 2026

Product Tie-In: Amplifiers, Mixers, Attenuators

IP3 Allocation in Receiver Design

IP3 budget allocation is a critical step in receiver design, determining the component specifications needed to meet the system linearity requirements.

Design Process

(1) Establish the system IIP3 requirement from the SFDR or blocking specification. (2) Create a cascade spreadsheet: list each stage with its gain and IIP3. Calculate each stage contribution to the cascade. (3) Iterate: if the cascade IIP3 is insufficient: increase the IIP3 of the dominant contributor (usually the last active stage), reduce the gain of early stages (this reduces the signal level at later stages), or add an attenuator before the critical stage. (4) Verify: simulate the complete receiver with the specified component IP3 values. Perform a two-tone test in simulation to confirm the system meets the IM3 specification.

IP3 Cascade Allocation

1/IIP3_total = Σ(G_n-1/IIP3_n) (linear)
IIP3_system = N_floor + 1.5×SFDR
Last stage often dominates cascade
Higher gain → worse cascade linearity
Budget: allocate highest IIP3 to last stage

Common Questions

Frequently Asked Questions

Should I use the worst-case or typical IP3 values?

For system design: use the worst-case (minimum) IP3 values from the datasheet. The cascade IP3 is dominated by the weakest link, and using typical values may leave insufficient margin. For production: add 3-6 dB margin to account for component variation and temperature effects.

How does the mixer IP3 affect the system?

The mixer is often the linearity bottleneck in the receiver because: it has conversion loss (not gain), which means the signal level at the mixer output is relatively high. The mixer IIP3 must be high enough to handle the amplified signal without generating IM3. In practice: passive mixers (diode ring, FET switch) have higher IIP3 (+15 to +30 dBm) than active mixers (+5 to +15 dBm).

What about cascading IP2?

IP2 cascades similarly: 1/IIP2_total = 1/IIP2_1 + G1/IIP2_2 + ... IP2 is critical for direct-conversion receivers where the second-order product (at f1-f2) falls at DC/baseband. Requirements: IIP2 > +40 to +70 dBm for direct-conversion cellular receivers. This is achieved using balanced mixer topologies and digital DC offset calibration.

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