Thermal Management and Reliability Thermal Design for RF Informational

How do I design the thermal via array under an RF power device on a PCB?

Q: How many vias do I need?

The number depends on the total power and the allowed thermal resistance. For 10W dissipation, T_j_max = 150°C, T_amb = 50°C: total allowed R_θ = 100/10 = 10 °C/W. If R_θJC = 3 °C/W and R_θSA = 2 °C/W: remaining for PCB: R_θ_via = 10 - 3 - 2 = 5 °C/W. For 1.6 mm FR4 with 0.3 mm plated vias: approximately 20-30 vias are needed. Rule of thumb: fill the entire thermal pad area with vias at the minimum pitch your fab can support (typically 1.0-1.2 mm pitch).

Q: Should vias be in-pad or around the pad?

In-pad (vias directly under the thermal pad) is strongly preferred: provides the shortest thermal path from the device to the bottom layer. The heat flows straight down through the vias. Around-pad (vias surrounding the thermal pad) forces the heat to spread laterally through the top copper before reaching the vias, adding thermal resistance. In-pad vias require: filled and capped vias (to provide a flat surface for device soldering), or careful solder mask design (to prevent solder wicking into open vias during reflow).

Q: Does via plating thickness matter?

Yes. Thicker copper plating = more copper cross-section = lower thermal resistance per via. Standard plating: 25 μm. Heavy plating: 50 μm (approximately 50% more copper area, ~33% lower thermal resistance per via). The minimum plating thickness should be 25 μm for reliable thermal performance. Some high-power designs specify 50 μm minimum barrel plating. For copper-filled vias: the plating thickness is irrelevant (the entire via is solid copper).

A thermal via array is a grid of plated through-holes under the device thermal pad on a PCB, providing a low-resistance thermal path from the top copper layer to the bottom copper layer (and optionally to a heat sink mounted on the bottom): (1) Purpose: the PCB substrate (FR4, Rogers, etc.) has poor thermal conductivity (0.2-0.5 W/m·K for FR4). Without thermal vias: the heat must spread laterally through the thin copper layers, creating a high thermal resistance. With thermal vias: the heat flows vertically through the copper-filled (or copper-plated) vias, which have much higher thermal conductivity. (2) Design parameters: via diameter: 0.3-0.5 mm (12-20 mil) is typical. Smaller vias have higher thermal resistance per via but can be packed more densely. Via pitch: 1.0-1.5 mm (40-60 mil) center-to-center. Tighter pitch = more vias per unit area = lower thermal resistance. Via plating: standard plated through-hole (PTH): 25-50 μm copper wall. Thermal conductivity of copper wall: good, but the via core is hollow (filled with air or solder). Filled vias (copper-filled or epoxy-filled): provide even lower thermal resistance. Copper-filled vias have the best thermal performance. (3) Thermal resistance of a via array: R_θ_via_array ≈ (L / (k_Cu × A_Cu × N)). Where L = PCB thickness (typically 1.6 mm), k_Cu = thermal conductivity of copper (390 W/m·K), A_Cu = cross-sectional area of copper per via (π × (d_outer² - d_inner²) / 4 for plated vias), and N = number of vias. Example: 25 plated vias, 0.3 mm drill, 0.05 mm plating, PCB thickness 1.6 mm. Copper annulus area per via: π × (0.15² - 0.10²) = 0.0393 mm² = 3.93 × 10^-8 m². Total copper area: 25 × 3.93 × 10^-8 = 9.82 × 10^-7 m². R_θ = 1.6 × 10^-3 / (390 × 9.82 × 10^-7) = 1.6e-3 / 3.83e-4 = 4.2 °C/W. With copper-filled vias (full 0.3 mm diameter): A_Cu = π × 0.15² = 7.07 × 10^-8 m² per via. Total: 25 × 7.07e-8 = 1.77e-6 m². R_θ = 1.6e-3 / (390 × 1.77e-6) = 2.3 °C/W (significantly better). (4) Additional guidelines: place vias directly under the device thermal pad (not offset). Ensure vias connect to a large copper pour on the bottom layer (for heat spreading). If using a heat sink on the bottom: solder or thermally bond the heat sink directly to the bottom copper pour. Avoid solder wicking into open vias during reflow (use solder mask tenting or via filling).

Category: Thermal Management and Reliability

Updated: April 2026

Product Tie-In: Heat Sinks, Thermal Materials, Power Devices

Thermal Via Array Design

Thermal via arrays are essential for any PCB-mounted RF power device, as the substrate itself is a thermal insulator compared to the metal paths.

Via Fill Options

(1) Open (unfilled) vias: standard PTH process. Pros: lowest cost, standard fabrication. Cons: hollow core (only the copper wall conducts heat). Risk of solder wicking during reflow. Mitigate with solder mask tenting. (2) Epoxy-filled vias: filled with thermally conductive (or non-conductive) epoxy, then plated over. Pros: no solder wicking, provides a planar surface for device mounting. Cons: epoxy fill has poor thermal conductivity (0.5-2 W/m·K), so the thermal improvement over open vias is modest. (3) Copper-filled vias: filled with electroplated copper. Pros: best thermal performance (solid copper core). Cons: expensive (requires multiple plating steps), limited to small via diameters (< 0.3 mm for reliable fill). Used in high-performance applications where thermal performance justifies the cost.

Via Array Thermal Design

R_θ_via ≈ L/(k_Cu × A_Cu × N)
PTH: A_Cu = π(r_out² - r_in²) per via
Filled: A_Cu = πr² per via (2× better)
Via pitch: 1.0-1.5 mm typical
25 filled vias, 1.6mm PCB: R_θ ≈ 2.3 °C/W

Common Questions

Frequently Asked Questions

How many vias do I need?

The number depends on the total power and the allowed thermal resistance. For 10W dissipation, T_j_max = 150°C, T_amb = 50°C: total allowed R_θ = 100/10 = 10 °C/W. If R_θJC = 3 °C/W and R_θSA = 2 °C/W: remaining for PCB: R_θ_via = 10 - 3 - 2 = 5 °C/W. For 1.6 mm FR4 with 0.3 mm plated vias: approximately 20-30 vias are needed. Rule of thumb: fill the entire thermal pad area with vias at the minimum pitch your fab can support (typically 1.0-1.2 mm pitch).

Should vias be in-pad or around the pad?

In-pad (vias directly under the thermal pad) is strongly preferred: provides the shortest thermal path from the device to the bottom layer. The heat flows straight down through the vias. Around-pad (vias surrounding the thermal pad) forces the heat to spread laterally through the top copper before reaching the vias, adding thermal resistance. In-pad vias require: filled and capped vias (to provide a flat surface for device soldering), or careful solder mask design (to prevent solder wicking into open vias during reflow).

Does via plating thickness matter?

Yes. Thicker copper plating = more copper cross-section = lower thermal resistance per via. Standard plating: 25 μm. Heavy plating: 50 μm (approximately 50% more copper area, ~33% lower thermal resistance per via). The minimum plating thickness should be 25 μm for reliable thermal performance. Some high-power designs specify 50 μm minimum barrel plating. For copper-filled vias: the plating thickness is irrelevant (the entire via is solid copper).

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