How do I design the thermal via array under an RF power device on a PCB?
Thermal Via Array Design
Thermal via arrays are essential for any PCB-mounted RF power device, as the substrate itself is a thermal insulator compared to the metal paths.
Frequently Asked Questions
How many vias do I need?
The number depends on the total power and the allowed thermal resistance. For 10W dissipation, T_j_max = 150°C, T_amb = 50°C: total allowed R_θ = 100/10 = 10 °C/W. If R_θJC = 3 °C/W and R_θSA = 2 °C/W: remaining for PCB: R_θ_via = 10 - 3 - 2 = 5 °C/W. For 1.6 mm FR4 with 0.3 mm plated vias: approximately 20-30 vias are needed. Rule of thumb: fill the entire thermal pad area with vias at the minimum pitch your fab can support (typically 1.0-1.2 mm pitch).
Should vias be in-pad or around the pad?
In-pad (vias directly under the thermal pad) is strongly preferred: provides the shortest thermal path from the device to the bottom layer. The heat flows straight down through the vias. Around-pad (vias surrounding the thermal pad) forces the heat to spread laterally through the top copper before reaching the vias, adding thermal resistance. In-pad vias require: filled and capped vias (to provide a flat surface for device soldering), or careful solder mask design (to prevent solder wicking into open vias during reflow).
Does via plating thickness matter?
Yes. Thicker copper plating = more copper cross-section = lower thermal resistance per via. Standard plating: 25 μm. Heavy plating: 50 μm (approximately 50% more copper area, ~33% lower thermal resistance per via). The minimum plating thickness should be 25 μm for reliable thermal performance. Some high-power designs specify 50 μm minimum barrel plating. For copper-filled vias: the plating thickness is irrelevant (the entire via is solid copper).