How do I debug a PLL that will not lock to the desired frequency?

Debugging a PLL (Phase-Locked Loop) that will not lock to the desired frequency requires systematic investigation of the reference input, feedback divider, phase detector, loop filter, and VCO. The most common causes of PLL lock failure are: missing or inadequate reference signal (verify the reference oscillator is present, at the correct frequency and power level, and properly connected to the PLL's reference input), incorrect programming (verify the N and R divider values programmed via SPI/I2C produce the correct output frequency; verify the register initialization sequence follows the datasheet's recommended procedure, particularly the order of register writes), VCO frequency out of range (the VCO's tuning range must include the desired output frequency; check the VCO tuning voltage is within the expected range, typically 0.5-4.5V, not railed at 0V or Vdd), loop filter component values incorrect (wrong values cause the loop bandwidth or phase margin to be outside the range where the loop can acquire lock), power supply issues (insufficient or noisy power supply prevents the charge pump, VCO, or dividers from operating correctly; check all Vcc pins for correct voltage and adequate decoupling), and damaged components (ESD damage to the charge pump or VCO). Debug procedure: (1) verify power and reference input, (2) read back PLL registers to confirm programming, (3) measure PLL lock detect output (if available), (4) measure the VCO tuning voltage (indicates whether the loop is trying to lock), (5) measure the VCO output frequency directly to verify the VCO is operational.