Spurious-Free Dynamic Range
Understanding ADC SFDR
ADC SFDR determines the receiver's ability to detect small signals near large signals. While SNR sets the broadband noise-limited sensitivity, SFDR determines whether a strong signal will generate spurious tones that mask a weak signal at a nearby frequency.
SFDR Limitations
- Harmonic distortion: ADC nonlinearity generates harmonics of the input signal. These are the most common spurious components.
- Clock jitter: Variations in sampling clock timing create noise and spurious tones, particularly at high input frequencies.
- DNL (Differential Nonlinearity): Errors in individual code transitions create signal-dependent spurious tones.
SFDR vs Input Frequency
SFDR degrades with input frequency because clock jitter and dynamic errors become more significant. A 14-bit ADC may achieve 85 dBc SFDR at 100 MHz input but only 70 dBc at 2 GHz input.
SFDR (dBFS) = SFDR(dBc) + (P_signal - P_FS)
Jitter-limited SFDR:
SFDR <= -20 log(2 pi f_in x t_jitter_rms)
Example: 100 fs jitter, 5 GHz input:
SFDR = -20 log(2 pi x 5e9 x 100e-15)
= -20 log(3.14e-3) = 50 dB
Frequently Asked Questions
What is ADC SFDR?
ADC SFDR is the ratio between the fundamental signal and the largest spurious component (usually a harmonic) in the digitized output. Higher SFDR means the ADC produces fewer spurious products that could be confused with real signals.
Why does SFDR matter for receivers?
A strong signal digitized by an ADC with poor SFDR generates spurious tones that fall at harmonic or intermodulation frequencies. If a weak desired signal happens to be at one of these frequencies, the spur masks it, effectively desensitizing the receiver.
How do you improve ADC SFDR?
Use a lower clock jitter source, select an ADC with better INL/DNL linearity, reduce the input signal bandwidth with anti-alias filtering, and operate below the ADC's full-scale input range to reduce harmonic distortion.