Phase Locked Loop Design
Understanding PLL Design
PLL design is at the heart of frequency synthesizer engineering. The PLL locks a VCO to a stable reference, providing the tunable frequency source for virtually every modern radio system.
PLL Design Parameters
- Reference frequency: Higher f_ref = lower N divider = better in-band phase noise. Limited by channel spacing in integer-N PLLs.
- Loop bandwidth: Sets the transition between reference-determined noise (in-band) and VCO noise (out-of-band). Typically 1-100 kHz.
- Loop filter order: 2nd-order for basic operation. 3rd-4th order for better reference spur rejection.
- Phase margin: 40-60 degrees for stable operation without excessive ringing.
Design Trade-offs
| Wide Loop BW | Narrow Loop BW |
|---|---|
| Fast settling (< 100 us) | Slow settling (> 1 ms) |
| Less VCO noise suppression | More VCO noise suppression |
| Higher reference spurs | Lower reference spurs |
| Better reference noise tracking | More VCO noise influence |
Frequently Asked Questions
What is PLL loop bandwidth?
Loop bandwidth is the frequency where the PLL transitions from tracking the reference (in-band) to following the VCO (out-of-band). It determines settling time, noise profile, and spur levels. Typically 1-100 kHz.
How do I choose loop bandwidth?
Wider BW for fast switching applications (radar, frequency hopping). Narrower BW for low phase noise (communications). Set BW at the crossover where reference noise (scaled by 20logN) equals VCO noise for optimal overall phase noise.
What causes reference spurs?
Reference spurs are caused by charge pump leakage current and mismatch modulating the VCO at the reference frequency. Higher loop filter order provides more filtering of reference spurs. Fractional-N PLLs have additional quantization noise spurs.