Electronic Design Automation

DC Analysis

Q: How does a SPICE simulator solve the DC operating point?

The simulator opens every capacitor and shorts every inductor, leaving a resistive nonlinear network. It assembles the modified nodal analysis (MNA) equations f(v) = 0, then linearizes each nonlinear device about the present voltage guess using its small-signal conductance (the Jacobian). Newton-Raphson iteration solves the linearized system, updates the node voltages, and repeats until both the voltage change between iterations falls below reltol times the node value plus vntol (default 1 microvolt) and the residual currents satisfy abstol (default 1 picoamp). A typical RF bias point converges in 5 to 20 iterations. Diode and transistor exponentials are limited per iteration to avoid numerical overflow.

Q: Why does my DC analysis fail to converge and how do I fix it?

Non-convergence usually comes from the steep exponential I-V curves of forward-biased junctions, floating nodes with no DC path to ground, or positive-feedback loops that have no stable equilibrium. The first remedy is GMIN stepping, where the simulator adds a small conductance (default GMIN = 1e-12 S) from every node to ground and ramps it down. If that fails, source stepping ramps every supply from zero to its final value in fractions. Practical fixes include adding a large resistor from every floating node to ground, supplying realistic .NODESET or .IC initial guesses near the expected bias, loosening RELTOL from 1e-3 to 1e-2, and raising ITL1 (the DC iteration limit) from 100 to 500.

Q: What is the difference between a DC operating point and a DC sweep?

A DC operating point (.OP) computes one steady-state solution at the nominal supply and input conditions, reporting node voltages, branch currents, and the small-signal model parameters (gm, gds, Cgs) that AC and S-parameter analyses then use. A DC sweep (.DC) repeats the operating-point solve while stepping one or more sources across a range, for example sweeping VGS from 0 to 3 V to plot the IDS-VGS transfer curve, or sweeping VDS to trace the output I-V family that defines the load line. The sweep reuses the previous step's solution as the initial guess, which both speeds convergence and naturally traces hysteresis-free curves.

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Before any frequency-domain simulation can run, a circuit solver must find the steady-state DC voltages and currents that every device settles into with no signal applied. DC analysis performs this by opening all capacitors and shorting all inductors, reducing the circuit to a nonlinear resistive network, then iterating the nodal equations until they converge. The resulting operating point fixes each transistor's transconductance and output conductance, which in turn become the small-signal model that AC, noise, S-parameter, and harmonic-balance analyses are linearized around. A wrong or non-converged bias point invalidates every downstream result, which is why DC analysis is the first and most fundamental step in EDA circuit simulation.

Category: Electronic Design Automation

SPICE card: .OP / .DC

Solver: Newton-Raphson

How the Operating Point Is Solved

Every transient, AC, and large-signal simulation begins with a DC analysis because the device equations are nonlinear and must be linearized about a known bias state. The simulator first builds the modified nodal analysis (MNA) matrix from Kirchhoff's current law, treating capacitors as open circuits and inductors as short circuits so that only conductances, controlled sources, and DC supplies remain. The system of equations f(v) = 0 is generally nonlinear because diodes and transistors contribute exponential or square-law current terms, so a direct matrix solve is not possible.

Newton-Raphson iteration handles the nonlinearity. At each step the solver evaluates every device's current and its derivative (the small-signal conductance), assembles the Jacobian matrix, and solves a linearized system for a voltage update. The process repeats until consecutive node voltages and branch currents change by less than the tolerance settings. For a well-conditioned RF bias network this takes only a handful of iterations, but circuits with sharp junction nonlinearities or feedback can stall, which is when GMIN stepping or source stepping is invoked.

Once the operating point is found, the solver reports node voltages, supply currents, and the linearized device parameters such as g_m, g_ds, and the junction capacitances. A power-amplifier designer reads these directly to confirm a GaN HEMT is biased in its target class, while the AC and S-parameter engines consume the same numbers automatically to build the small-signal equivalent circuit.

DC Operating-Point and Convergence Equations

Nonlinear nodal system (reactances removed):
f(v) = G · v + i_NL(v) − i_src = 0

Newton-Raphson update (iteration k):
v^(k+1) = v^(k) − J⁻¹(v^(k)) · f(v^(k)), where J_ij = ∂f_i / ∂v_j

Diode current and its Jacobian conductance:
I_D = I_S(e^V/nV_T − 1), g_d = ∂I_D/∂V ≈ I_D / (nV_T), V_T ≈ 25.85 mV @ 300 K

Convergence test (per node):
|v_n^(k+1) − v_n^(k)| < RELTOL × |v_n| + VNTOL AND |i_residual| < ABSTOL

Typical SPICE defaults: RELTOL = 1×10⁻³, VNTOL = 1 μV, ABSTOL = 1 pA, GMIN = 1×10⁻¹² S, ITL1 = 100 DC iterations.

DC Analysis Modes and Defaults

Mode / Setting	SPICE Card	What It Does	Typical Default	When to Adjust
Operating point	.OP	One bias solution + small-signal params	nominal supplies	Always (auto before AC/TRAN)
DC sweep	.DC src start stop step	Steps a source, traces I-V curves	linear sweep	Load-line, transfer curves
Transfer function	.TF	DC gain, input/output resistance	n/a	Bias-network sensitivity
GMIN stepping	auto / GMIN	Ramps shunt conductance to aid solve	1×10⁻¹² S	Junction-rich circuits stall
Source stepping	auto / .OPTIONS	Ramps supplies 0 → final	fallback	GMIN stepping fails
Initial guess	.NODESET / .IC	Seeds node voltages near solution	0 V	Multi-stable / feedback nodes

Common Questions

Frequently Asked Questions

How does a SPICE simulator solve the DC operating point?

It opens every capacitor and shorts every inductor, leaving a nonlinear resistive network described by the modified nodal analysis equations f(v) = 0. Each device is linearized about the current guess via its small-signal conductance (the Jacobian), and Newton-Raphson iterates until the node-voltage change is below RELTOL × |v| + VNTOL (1 μV) and residual currents satisfy ABSTOL (1 pA). A typical RF bias point converges in 5 to 20 iterations, with junction exponentials limited each step to prevent overflow.

Why does my DC analysis fail to converge and how do I fix it?

The usual culprits are steep forward-biased junction curves, floating nodes with no DC path to ground, or feedback loops with no stable equilibrium. GMIN stepping adds a small shunt conductance (default 1×10⁻¹² S) to every node and ramps it down; source stepping ramps the supplies from zero if that fails. Practical fixes: add a large resistor from any floating node to ground, supply .NODESET or .IC guesses, loosen RELTOL to 1×10⁻², and raise ITL1 from 100 to 500.

What is the difference between a DC operating point and a DC sweep?

An operating point (.OP) computes one steady-state solution at nominal conditions and reports the small-signal model (g_m, g_ds, capacitances) used by AC and S-parameter runs. A DC sweep (.DC) repeats that solve while stepping a source, for example V_GS from 0 to 3 V for a transfer curve or V_DS to trace the output I-V family that defines the load line. Each step reuses the prior solution as its initial guess, speeding convergence and tracing smooth curves.

Related Terms

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