Semiconductor Fabrication

Damascene

Q: Why did the industry switch from aluminum subtractive etch to copper damascene?

Copper has roughly 40 percent lower bulk resistivity than aluminum (1.68 vs 2.65 micro-ohm-cm) and far better electromigration resistance, but copper cannot be plasma-etched cleanly because its halide byproducts are non-volatile at practical temperatures. Damascene sidesteps the etch problem entirely: instead of depositing a metal blanket and etching the wires, you etch the wire pattern into the dielectric, fill it with copper, and polish back. This inlaid approach made copper interconnect manufacturable at the 0.18 micron node and below, cutting RC interconnect delay and improving current density limits for dense RFIC and MMIC metal stacks.

Q: What is the difference between single and dual damascene?

Single damascene patterns and fills one feature per metallization pass, so a via layer and the metal line above it are each formed in separate etch, fill, and CMP cycles. Dual damascene forms the via and the overlying trench in a single copper fill and a single CMP step, using either a via-first or trench-first lithography sequence to define both depths before plating. Dual damascene halves the number of CMP and barrier deposition steps per interconnect level, which is why it dominates production back-end-of-line flows; single damascene is still used for the bottom-most contact level and for some specialty thick-metal RF layers.

Q: Why is a barrier and seed layer required before copper electroplating?

Copper diffuses rapidly through silicon and silicon dioxide and acts as a deep-level trap that destroys device performance, so a conformal diffusion barrier such as tantalum nitride or titanium nitride (typically 2 to 10 nm) must line every trench and via wall before copper is introduced. Electroplating also needs an electrically continuous, conductive starting surface, so a PVD or ALD copper seed of roughly 20 to 100 nm is deposited over the barrier to carry plating current and nucleate void-free superfill. Poor barrier step coverage causes copper poisoning and via voiding, the two most common damascene yield failures.

/DAM-uh-seen/

Named after the inlaid metalwork of Damascus, this back-end-of-line copper interconnect process etches trenches and vias into an inter-layer dielectric, lines them with a diffusion barrier and copper seed, fills the features with electroplated copper, then removes the overburden by chemical mechanical polishing so the metal sits flush with the dielectric. Because copper cannot be plasma-etched cleanly, this inlaid approach replaced subtractive aluminum etching at the 0.18 µm node and is the standard route for low-resistance, electromigration-robust wiring in dense RFIC and MMIC metal stacks operating into the millimeter-wave bands.

Category: Semiconductor Fabrication

Fill Metal: Electroplated Cu

Cu Resistivity: 1.68 µΩ·cm

How the Inlaid Copper Process Works

The damascene flow inverts the classic subtractive metal process. Rather than blanket-depositing a metal film and plasma-etching away everything that is not a wire, the wire pattern itself is etched as a void into the inter-layer dielectric (ILD), typically a fluorine- or carbon-doped low-k oxide. That void is then conformally lined with a diffusion barrier (tantalum nitride or titanium nitride, 2 to 10 nm) and a copper seed layer (20 to 100 nm of PVD or ALD copper), after which an electrolytic copper bath performs a bottom-up superfill that closes the trench from the floor upward without trapping a seam or void. A bulk overburden of copper is plated above the surface, then a chemical mechanical polish removes everything down to the dielectric, leaving inlaid copper conductors planar with the ILD.

This sequence solved the central problem that blocked copper for decades: its volatile-halide etch byproducts are non-volatile at wafer-safe temperatures, so copper wires cannot be patterned by reactive-ion etch the way aluminum is. By patterning the dielectric instead and filling afterward, the process never has to etch the copper. The payoff is roughly 40 percent lower line resistance than aluminum and order-of-magnitude better electromigration lifetime, both critical for the tightly packed, high-current-density metal routing of modern RF integrated circuits.

For RF and millimeter-wave designers, damascene metallization sets the achievable inductor Q, transmission-line loss, and current-handling of the upper redistribution layers. The copper line resistivity rises above the 1.68 µΩ·cm bulk value as line widths shrink toward the electron mean free path (about 39 nm in copper), because grain-boundary and sidewall scattering dominate; this size effect is a first-order constraint when laying out narrow on-chip RF feedlines and matching networks.

Single Versus Dual Damascene

Single damascene forms one feature per cycle, so a via and the metal line above it each get a separate etch, barrier, fill, and CMP pass. Dual damascene forms both the via and the overlying trench with a single copper fill and a single polish, using a via-first or trench-first lithography order to define the two depths before plating. Halving the CMP and barrier steps per level is why dual damascene dominates production back-end-of-line stacks; single damascene survives for the bottom contact level and certain thick-metal RF layers.

Governing Relationships

Inlaid line resistance:
R = ρ_eff × L / (W × H)

Size-effect resistivity (Fuchs-Sondheimer):
ρ_eff ≈ ρ₀ × [1 + (3/8)(1 − p) × λ / W]

Electromigration lifetime (Black's equation):
MTTF = A × J⁻ⁿ × e^{(E_a / k T)}

Where ρ₀ = 1.68 µΩ·cm (bulk Cu), λ ≈ 39 nm (electron mean free path), p = surface specularity (0 to 1), W = line width, H = line height, J = current density, n ≈ 2 for Cu, E_a ≈ 0.9 eV for damascene copper. Example: for a 100 nm wide line with fully diffuse surfaces (p = 0), the surface-scattering term alone gives ρ_eff ≈ 1.93 µΩ·cm, about 1.15× bulk; grain-boundary (Mayadas-Shatzkes) scattering adds further, so measured narrow-line copper typically runs 2.2 to 3.0 µΩ·cm.

Process and Material Comparison

Attribute	Aluminum Subtractive	Single Damascene Cu	Dual Damascene Cu
Patterning method	Etch the metal	Etch dielectric, inlay metal	Etch dielectric, inlay metal
Bulk resistivity	2.65 µΩ·cm	1.68 µΩ·cm	1.68 µΩ·cm
Via + line per cycle	Separate	Separate	Combined (one fill, one CMP)
Barrier needed	Minimal (Ti/TiN)	TaN/TiN, 2 to 10 nm	TaN/TiN, 2 to 10 nm
CMP steps per level	None (etchback)	2	1
Electromigration E_a	~0.6 eV	~0.9 eV	~0.9 eV
Practical node	≥ 0.25 µm	0.18 µm and below	0.13 µm and below

Common Questions

Frequently Asked Questions

Why did the industry switch from aluminum subtractive etch to copper damascene?

Copper has about 40 percent lower bulk resistivity than aluminum (1.68 vs 2.65 µΩ·cm) and far better electromigration resistance, but its halide etch byproducts are non-volatile at wafer-safe temperatures, so it cannot be plasma-etched cleanly. Damascene avoids etching copper entirely: pattern the dielectric, fill with copper, polish back. That made copper manufacturable at 0.18 µm and below, cutting RC delay and raising current limits for dense RFIC and MMIC metal stacks.

What is the difference between single and dual damascene?

Single damascene patterns and fills one feature per pass, so a via and the line above it each take separate etch, fill, and CMP cycles. Dual damascene forms the via and overlying trench in one copper fill and one CMP, using a via-first or trench-first sequence to define both depths before plating. Dual damascene halves the CMP and barrier steps per level, so it dominates production; single damascene is kept for the bottom contact level and some thick-metal RF layers.

Why is a barrier and seed layer required before copper electroplating?

Copper diffuses rapidly through silicon and SiO₂ and creates deep-level traps that ruin devices, so a conformal barrier (TaN or TiN, 2 to 10 nm) must line every trench and via before copper is introduced. Electroplating also needs a continuous conductive surface, so a 20 to 100 nm PVD or ALD copper seed carries plating current and nucleates void-free superfill. Poor barrier step coverage causes copper poisoning and via voiding, the two most common damascene yield failures.

Related Terms

← DAMA Damping →