Power & Thermal

Current Limiting

Q: What is the difference between constant current limiting and foldback current limiting?

Constant (brick-wall) limiting holds the output at a fixed maximum current I_limit regardless of how far the load resistance drops, so under a dead short the regulator still sources the full I_limit at near-zero output voltage. That product of full current and the entire input-to-output voltage is dissipated in the pass device, which is the worst-case stress point. Foldback limiting instead reduces the allowed current as the output voltage collapses, so a hard short might only draw 25 to 40 percent of the nominal limit. Foldback dramatically cuts pass-device dissipation during a short, which is why it is preferred for linear bias regulators feeding GaN and GaAs amplifiers, but it must be designed so the foldback knee does not re-trigger during normal startup into a large bypass capacitor.

Q: How do you set the current limit for a GaN HEMT drain supply?

Set the hard current limit roughly 15 to 30 percent above the maximum expected drain current at peak RF output, including the quiescent class-AB bias plus the RF-induced DC current rise. For a 50 W GaN device biased at 28 V with about 1.8 A quiescent and rising to roughly 3.5 A at saturation, a limit near 4.2 to 4.5 A is typical. The limit must clear the in-rush from the drain bypass capacitance at turn-on, so the supply usually uses a soft-start ramp or a current limit that is sequenced after the negative gate bias is established. Setting the limit too tight clips RF peaks and compresses output power; setting it too loose lets a gate-bias failure drive the device into runaway before the limit acts.

Q: How fast must a current limit respond to protect an RF transistor?

Response time must beat the thermal time constant of the transistor die, which for a small mm-wave gate finger can be on the order of microseconds, while a packaged power bar may tolerate tens to hundreds of microseconds. Analog foldback and pass-transistor limiters react in 1 to 10 microseconds, fast enough for most package-level events. Pure thermal protection (sensing case temperature) reacts in seconds and only guards against slow average overload, not a fast short or oscillation. For the fastest events, designers add a series fuse or an electronic crowbar that latches off within microseconds once a current threshold is exceeded, accepting that recovery requires a manual or sequenced reset.

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Capping the maximum current a bias supply or rail will deliver to an active device is the last line of defense for an RF power amplifier when a fault, output mismatch, or overdrive pushes draw beyond design limits. The protection circuit detects when current reaches a preset threshold I_limit and then either clamps the supply, reduces (folds back) the allowed current, or latches the rail off, holding the device inside its safe operating area. For a GaN HEMT drain rail, this prevents the positive feedback loop where rising drain current heats the junction, which raises leakage and bias current further, leading to thermal runaway and irreversible die failure. The limit is set above peak operating current so it never clips normal RF envelopes, yet tight enough that a gate-bias loss or a 6:1 load VSWR cannot drive the part to destruction.

Category: Power & Thermal

Typical headroom: 15 to 30% above I_peak

Response time: 1 to 10 μs

How Current Limiting Protects RF Power Devices

A bias supply feeding an RF power transistor normally behaves as a voltage source: it holds the drain or collector rail at a fixed level and lets the device draw whatever current its operating point demands. That works until something goes wrong. A connector that opens into a high VSWR, an oscillation that drives the stage into saturation, a shorted bypass capacitor, or a gate-bias supply that drops out can all push the device current far above its rated maximum. Without protection, the supply simply delivers that current, and the transistor either melts a bond wire, cracks the die from thermal stress, or enters thermal runaway. Current limiting converts the supply from a pure voltage source into a current-bounded source above a chosen threshold.

The threshold is chosen against the device safe operating area. For a class-AB stage you must allow the full quiescent current plus the DC current that the RF drive pulls up at peak envelope. A 50 W GaN device biased at 28 V might idle near 1.8 A and rise toward 3.5 A at saturation, so a limit around 4.2 to 4.5 A leaves margin for envelope peaks while still catching a fault. Set the limit too low and the supply sags on RF peaks, compressing output power and degrading linearity; set it too high and the protection never engages before the junction is destroyed. The sequencing matters too: the negative gate bias must be present before the drain rail ramps, so most designs combine current limiting with a soft-start and bias sequencing.

Once the limit acts, the supply must also survive its own protection. The pass element absorbs the difference between the input voltage and the collapsed output voltage at full limit current, which is the worst-case dissipation point. This is why scheme selection (constant versus foldback) is itself a thermal-design decision, not just a control-loop choice.

Constant-Current Versus Foldback Limiting

A constant or brick-wall limiter holds output current at I_limit no matter how low the load resistance falls, so a dead short still draws full current at near-zero output voltage and the pass device dissipates the entire input-to-output voltage at full current. Foldback limiting reduces the permitted current as the output voltage collapses, so a hard short might draw only 25 to 40 percent of nominal, slashing pass-device stress. Foldback is preferred for linear bias regulators feeding sensitive amplifiers, with the caveat that the foldback knee must clear normal startup into a large bypass capacitor or it can latch into a false short.

Governing Equations

Sense-resistor current limit:
I_limit ≈ V_BE(on) / R_sense (≈ 0.65 V / R_sense for a BJT sense)

Foldback short-circuit current:
I_SC = I_limit × R₂ / (R₁ + R₂) (divider sets foldback ratio)

Worst-case pass-device dissipation:
P_diss = (V_in − V_out) × I_out → V_in × I_limit at short

Bias headroom rule:
I_limit ≈ (1.15 to 1.30) × I_peak, where I_peak = I_q + ΔI_RF

Example: 28 V GaN rail, I_peak ≈ 3.5 A → I_limit ≈ 4.4 A. Under a short, a brick-wall design dissipates 28 V × 4.4 A ≈ 123 W in the pass device; a 0.3 foldback ratio cuts that to ≈ 37 W.

Protection Scheme Comparison

Scheme	Response Time	Short-Circuit Stress	Auto-Recovery	Best Use
Constant (brick-wall)	1 to 10 μs	Highest (V_in × I_limit)	Yes	Low-dropout rails, short V_in-V_out
Foldback	1 to 10 μs	Low (25 to 40% of limit)	Yes (watch startup)	Linear bias for GaN / GaAs PAs
Latch-off / crowbar	< 1 to 5 μs	Lowest (rail opens)	No (manual reset)	Fast fault, oscillation lockout
Series fuse	ms to s	Until fuse clears	No (replace)	Catastrophic backstop only
Thermal foldback	Seconds	N/A (slow average)	Yes	Long-term overload, not fast faults

Common Questions

Frequently Asked Questions

What is the difference between constant current limiting and foldback current limiting?

Constant (brick-wall) limiting holds output at a fixed I_limit regardless of load, so a dead short still sources full current at near-zero output voltage and the pass device dissipates V_in × I_limit. Foldback reduces allowed current as output voltage collapses, so a hard short draws only 25 to 40% of nominal, cutting pass-device stress. Foldback is preferred for linear bias regulators feeding GaN and GaAs amplifiers, but the knee must clear startup into a large bypass capacitor.

How do you set the current limit for a GaN HEMT drain supply?

Set the hard limit roughly 15 to 30% above maximum expected drain current at peak RF output (quiescent plus RF-induced DC rise). A 50 W GaN device at 28 V idling near 1.8 A and rising to about 3.5 A at saturation wants a limit near 4.2 to 4.5 A. The limit must clear drain-bypass in-rush at turn-on, so it is sequenced after the negative gate bias is set. Too tight clips RF peaks and compresses power; too loose lets a gate-bias failure drive runaway before the limit acts.

How fast must a current limit respond to protect an RF transistor?

It must beat the die thermal time constant, which for a small mm-wave gate finger is on the order of microseconds while a packaged power bar tolerates tens to hundreds of microseconds. Analog foldback and pass-transistor limiters react in 1 to 10 μs, fast enough for most package events. Case-temperature thermal protection reacts in seconds and only guards slow overload. For the fastest events, a series fuse or electronic crowbar latches off within microseconds, accepting that recovery needs a manual or sequenced reset.

Related Terms

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