Why does the complementary cross-coupled core have better phase noise than the NMOS-only core?

The complementary core stacks an NMOS pair and a PMOS pair and reuses the same bias current twice, so it produces roughly double the negative conductance for a given current. This lets it reach the same loop gain at half the current, or deliver a larger oscillation amplitude at the same current. Because phase noise in the thermal region scales as 1/A squared with oscillation amplitude A, the larger swing of the complementary core directly lowers the noise floor. The complementary topology also forces a more symmetric rise and fall waveform, which reduces the up-conversion of 1/f device noise into close-in phase noise by minimizing the impulse-sensitivity-function dc term. The cost is reduced voltage headroom, since both NMOS and PMOS sit in the same current path, so very low supply voltages can favor the NMOS-only core instead.

What sets the oscillation frequency and how is it tuned in a cross-coupled VCO?

The oscillation frequency is set by the LC tank resonance, f0 = 1/(2 pi times the square root of L times C), where C is the sum of the fixed capacitance, the device parasitic capacitance, and the tunable varactor capacitance. In a voltage-controlled oscillator the varactor capacitance is swept by the tuning voltage to move f0; a typical integrated RF VCO covers a 15 to 30 percent tuning range. Wider tuning is achieved with a switched-capacitor bank that selects coarse sub-bands while the varactor handles fine tuning, which keeps the VCO gain Kvco low and improves phase-noise robustness. The inductor is usually a planar spiral with a Q of 10 to 20, and tank Q dominates the achievable phase noise.

RF Design

Cross-Coupled Oscillator

Q: How much transconductance is needed to start a cross-coupled oscillator?

Startup requires the small-signal negative conductance from the pair to exceed the tank loss conductance, which translates to gm of each device being greater than the equivalent parallel tank conductance Gp. The classic rule is gm,crit = 1/Rp for an NMOS-only core and gm,crit = 1/(2 Rp) for a complementary NMOS plus PMOS core, where Rp is the equivalent parallel tank resistance. Designers typically size the devices for a loop gain of 2x to 3x above this critical value so that oscillation builds reliably across process, voltage, and temperature corners and over the full varactor tuning range. Too much excess gain wastes current and pushes the oscillator into a hard-limiting regime that can degrade phase noise, so the gain margin is a deliberate trade-off rather than a maximize-everything choice.

/kraws KUP-uld OS-uh-lay-ter/

Built from two transistors wired so each device drives the gate of the other, this differential topology forms a positive-feedback loop that synthesizes a negative resistance at its output. That negative resistance cancels the loss of the parallel LC tank, allowing a sustained oscillation to build from noise and settle into a steady amplitude. It is the workhorse core of monolithic RF voltage-controlled oscillators in CMOS and SiGe, prized for its simplicity, differential output, and excellent phase-noise-per-milliwatt at 1 to 30 GHz.

Category: RF Design

Typical range: 1 to 30 GHz

Tuning range: 15 to 30%

How Negative Resistance Sustains the Oscillation

A passive LC tank cannot oscillate forever on its own, because the finite resistance of the inductor and the load drains energy on every cycle. The cross-coupled pair fixes this by presenting an active negative resistance across the tank. With the drain of each transistor tied to the gate of its partner, a small voltage perturbation is amplified and fed back in phase, so the two-port looking into the differential drain nodes behaves as a resistance of value -2/gm, where gm is the transconductance of each device. When that magnitude is smaller than the equivalent parallel tank resistance, the net loss at the resonant frequency becomes negative and any noise at the tank's natural frequency grows exponentially.

Oscillation does not grow without bound. As the swing increases, the transistors spend more of each cycle in cutoff or triode, and the large-signal effective transconductance falls until the average negative conductance exactly equals the tank loss conductance. At that point the loop gain settles to unity and the amplitude stabilizes. This self-limiting behavior is why the design target is a small-signal loop gain of two to three, giving reliable startup with margin while leaving the steady-state amplitude set primarily by the bias current and the tank impedance rather than by an external limiter.

Two device arrangements dominate. The NMOS-only core uses a single differential pair and offers the most voltage headroom, which matters at low supplies. The complementary core stacks an NMOS pair and a PMOS pair to reuse the bias current and double the negative conductance per milliamp, trading headroom for lower phase noise and a more symmetric waveform. The choice between them is one of the central decisions in any integrated VCO design.

Startup and Amplitude Equations

Negative resistance looking into the pair:
R_neg = −2 / g_m

Startup (Barkhausen) condition:
g_m > 1 / R_p (NMOS core) · g_m > 1 / (2 R_p) (complementary core)

Oscillation frequency:
f₀ = 1 / (2π × √(L × C_tank))

Differential output amplitude (current-limited):
V_osc ≈ (4 / π) × I_bias × R_p

Leeson phase-noise model:
L(f_m) = 10·log[ 1 + (f₀ / (2 Q f_m))² ] × (F k T / P_s)

Where g_m = device transconductance, R_p = equivalent parallel tank resistance, C_tank = fixed + parasitic + varactor capacitance, I_bias = tail current, Q = loaded tank quality factor, f_m = offset frequency. Example: L = 0.5 nH, C_tank = 0.5 pF → f₀ ≈ 10.1 GHz.

Core Topology Comparison

Topology	g_m for startup	Headroom	Phase noise	Current efficiency	Best use
NMOS-only cross-coupled	g_m > 1/R_p	High	Good	Moderate	Low-supply CMOS VCOs
Complementary (NMOS+PMOS)	g_m > 1/(2R_p)	Low	Best	High (current reuse)	Low-noise integer/fractional PLLs
Colpitts (single device)	Higher	High	Excellent (1/f up-conv. low)	Low	Discrete, low close-in noise
Class-C / tail-filtered	g_m > 1/R_p	Moderate	Excellent	Highest	FoM-optimized RF VCOs

Common Questions

Frequently Asked Questions

How much transconductance is needed to start a cross-coupled oscillator?

Startup needs the small-signal negative conductance to beat the tank loss, so g_m > 1/R_p for an NMOS-only core and g_m > 1/(2R_p) for a complementary core, where R_p is the equivalent parallel tank resistance. Designers size for a loop gain of 2x to 3x above this critical value so oscillation builds reliably across process, voltage, temperature, and the full varactor range. Excess gain wastes current and hardens limiting, which can hurt phase noise, so the margin is a deliberate trade-off.

Why does the complementary core have better phase noise than the NMOS-only core?

The complementary core reuses the bias current through both an NMOS and a PMOS pair, roughly doubling negative conductance per milliamp, so it can reach the same loop gain at half the current or a larger swing at the same current. Since thermal-region phase noise scales as 1/V_osc², the bigger swing lowers the noise floor. Its more symmetric rise and fall also cuts 1/f up-conversion into close-in noise. The cost is reduced headroom, so very low supplies can favor the NMOS-only core.

What sets the frequency and how is it tuned in a cross-coupled VCO?

Frequency follows the tank resonance, f₀ = 1 / (2π√(L·C_tank)), where C_tank is fixed plus parasitic plus varactor capacitance. The varactor is swept by the tuning voltage for a typical 15 to 30% range. Wider coverage uses a switched-capacitor bank for coarse sub-bands while the varactor handles fine tuning, keeping K_vco low for better phase-noise robustness. Tank Q, often 10 to 20 for a planar spiral inductor, dominates achievable noise.

Related Terms

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