Wireless System Design

CompactPCI (cPCI)

Q: What is the difference between 3U and 6U CompactPCI boards?

The U designation refers to Eurocard height. A 3U board measures 100 mm by 160 mm and carries two connectors, J1 and J2, giving access to the full 64-bit PCI bus and 64-bit addressing. A 6U board measures 233.35 mm by 160 mm and adds connectors J3 through J5 (P3 to P5), providing roughly 315 extra rear-panel I/O pins for user-defined signals, telecom timing, or H.110 buses. For RF payloads, 3U is favored where board count and chassis depth must stay small, such as airborne SDR receivers, while 6U is chosen when a single slot must host an RF tuner, an FPGA digitizer, and dense rear I/O. Both share the same 2 mm hard-metric pin-and-socket connector per IEC 61076-4-101, which is rated for shock and vibration that a standard PCI card-edge connector cannot survive.

Q: How many slots can a single CompactPCI bus segment support?

A single CompactPCI bus segment supports a maximum of 8 slots: one system slot that holds the host CPU and PCI arbiter, plus up to 7 peripheral slots. This is a hard electrical limit because the 33 MHz parallel PCI backplane behaves as a transmission line, and each connector adds capacitive loading and a reflection. Beyond 8 loads the signal integrity at 33 MHz degrades below the PCI timing budget. To exceed 8 slots, designers use PCI-to-PCI bridges to create additional segments, or move to a serial-fabric successor such as CompactPCI Serial or OpenVPX. At the optional 66 MHz clock rate the practical limit drops to about 4 to 5 slots because the tighter setup and hold window leaves less margin for backplane reflections.

Q: Why is CompactPCI hot swap useful in RF and telecom systems?

PICMG 2.1 hot swap lets an operator insert or remove a board while the chassis stays powered, which is essential for carrier-grade telecom and field-serviceable RF systems that target 99.999 percent (five nines) availability. Staged connector pins control the sequence: long ground and precharge pins mate first to limit inrush current, medium power pins follow, and short bus signal pins connect last so the PCI bus is never disturbed mid-transaction. A blue ejector-handle LED and an ENUM# interrupt let the host software quiesce the board before extraction. In a redundant RF base station or radar processor, a failed digitizer or transceiver card can be replaced without dropping the link, avoiding a full chassis reboot and the associated outage.

/kuhm-pakt P-C-I/

Defined by the PICMG 2.0 specification, this rugged industrial bus standard maps the 32 or 64-bit PCI bus onto a 3U or 6U Eurocard form factor using a 2 mm hard-metric pin-and-socket backplane instead of fragile card-edge fingers. A single 33 MHz segment hosts up to 8 boards (1 system slot plus 7 peripheral slots), and PICMG 2.1 adds live insertion. The platform became the workhorse chassis for carrier telecom, defense electronics, and modular RF instrumentation, frequently pairing an FPGA digitizer card with a tuner front end to build a slot-based software defined radio. Built from COTS modules, it shortened development cycles for shock and vibration-hardened systems where standard desktop PCI could never survive.

Standard: PICMG 2.0

Form Factor: 3U / 6U Eurocard

Max Slots: 8 per segment

How CompactPCI Adapts PCI for Rugged RF Chassis

The standard, ratified by the PCI Industrial Computer Manufacturers Group (PICMG) in 1995, took the electrically identical 33 MHz parallel PCI bus that desktop computers used and repackaged it for industrial life. The biggest physical change is the connector. Where a desktop card relies on gold-plated edge fingers that wear and fret under vibration, a cPCI board uses a 2 mm two-part hard-metric connector per IEC 61076-4-101, with hundreds of gas-tight pin-and-socket contacts that hold up under the 0.1 g squared per Hz random vibration and 30 g shock common in airborne and shipboard racks. Boards plug vertically into a passive backplane and are retained by injector and ejector handles plus front-panel screws, so a slot card stays seated through transport and operation.

Electrically, the architecture preserves PCI bus semantics: a single 32-bit segment at 33 MHz delivers 132 MB/s of shared bandwidth, and a 64-bit segment doubles that to 264 MB/s. Because the backplane behaves as a loaded transmission line, the number of stubs is capped at 8 slots per segment so that reflections and capacitive loading stay inside the PCI setup-and-hold budget. The system slot holds the host CPU and the central PCI arbiter and clock distribution; peripheral slots hold the payload cards. To grow past 8 slots a designer cascades segments through a PCI-to-PCI bridge, which is exactly the moment many programs migrate to a serial-fabric successor.

Bus Bandwidth and Slot Loading

RF system architects size a cPCI chassis around two competing limits: aggregate backplane throughput and signal-integrity-limited slot count. A 6U digitizer sampling a 100 MHz IF at 250 MSPS with 16-bit words produces 500 MB/s of raw data per channel, which already swamps a single 33 MHz 64-bit shared segment. That mismatch is precisely why modern RF payloads on legacy cPCI carry an onboard FPGA to decimate, filter, and packetize data before it ever touches the shared bus, and why high-rate sensor processing migrated to point-to-point fabrics. The governing relations below let an engineer check whether a planned card count and clock rate keep the bus inside its timing margin.

Theoretical Bus Throughput:
BW = f_clk × (W / 8)
≈ 33.33 MHz × (64 / 8) = 266.6 MB/s (64-bit)

Practical Slot Limit (signal integrity):
N_slots ≈ t_budget / (t_flight + t_load) ≤ 8 at 33 MHz

Bridged Segment Expansion:
N_total = (N_seg × 7) + 1, per PCI-to-PCI bridge

Where f_clk = bus clock (33.33 or 66.67 MHz), W = data width in bits, t_budget = PCI cycle setup margin, t_flight ≈ backplane propagation delay (≈ 70 ps per cm), t_load = per-connector capacitive delay. Example: a 6U 64-bit segment yields 266.6 MB/s shared across ≤ 8 cards.

CompactPCI Versus Successor Form Factors

Standard	Spec Body	Backplane Type	Per-Slot Bandwidth	Max Slots / Segment	Typical RF Use
CompactPCI (cPCI)	PICMG 2.0	Parallel PCI, 33/66 MHz	132 to 264 MB/s (shared)	8	Telecom, rugged SDR control
CompactPCI Serial	PICMG CPCI-S.0	PCIe / SATA / USB fabric	Up to 8 GB/s (PCIe x8)	9 (star)	High-rate digitizer chassis
VPX / OpenVPX	VITA 46 / 65	Switched serial fabric	Multi-GB/s per lane	Profile dependent	Conduction-cooled radar, EW
VME / VME64x	ANSI/VITA 1	Parallel async bus	40 to 80 MB/s	21	Legacy defense, instrumentation
AdvancedTCA (ATCA)	PICMG 3.x	Switched serial fabric	Multi-GB/s per channel	14 (shelf)	Core telecom, baseband

Common Questions

Frequently Asked Questions

What is the difference between 3U and 6U CompactPCI boards?

A 3U board is 100 mm by 160 mm with two connectors (J1, J2) carrying the full 64-bit PCI bus. A 6U board is 233.35 mm by 160 mm and adds J3 to J5 for roughly 315 extra rear-panel I/O pins (user signals, telecom timing, H.110). RF designers pick 3U for shallow airborne SDR receivers and 6U when one slot must host a tuner, an FPGA digitizer, and dense rear I/O. Both use the same 2 mm hard-metric connector per IEC 61076-4-101.

How many slots can a single CompactPCI bus segment support?

A segment supports 8 slots maximum: 1 system slot (host CPU plus arbiter) and up to 7 peripheral slots. The 33 MHz parallel backplane acts as a transmission line, so each connector adds loading and reflection; beyond 8 loads the timing budget is exceeded. To grow further, designers add PCI-to-PCI bridges to create new segments. At the optional 66 MHz clock the practical limit drops to about 4 to 5 slots due to the tighter setup-and-hold window.

Why is CompactPCI hot swap useful in RF and telecom systems?

PICMG 2.1 hot swap lets a board be inserted or removed while the chassis stays powered, key for five-nines (99.999%) telecom and field-serviceable RF gear. Staged pins control the sequence: long ground and precharge pins mate first to limit inrush, power pins follow, and short bus pins connect last so the PCI bus is never disturbed mid-transaction. A blue handle LED and ENUM# interrupt let software quiesce the board, so a failed digitizer or transceiver card is swapped without dropping the link.

Related Terms

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