Electronic Design Automation

Courtyard

Q: What is courtyard excess and how does IPC-7351 set it?

Courtyard excess is the gap added on all sides between the maximum component body or land outline and the courtyard boundary. IPC-7351B defines it by density level: Level A (Most, maximum land protrusion) adds about 0.50 mm of excess, Level B (Nominal) adds 0.25 mm, and Level C (Least, for high-density designs) adds 0.10 mm. For a chip resistor the excess can drop to 0.10 to 0.15 mm, while large connectors and BGAs use the wider Level A value. The courtyard outline is conventionally drawn on a documentation layer such as Assembly or a dedicated Courtyard layer, on a 0.05 mm grid, with a thin 0.05 mm line so it never confuses the silkscreen or copper layers.

Q: How does courtyard violation checking work in a DRC?

Most EDA tools run a courtyard-overlap check as part of the design rule check. Each placed footprint carries a closed courtyard polygon, and the checker flags any two courtyards that overlap or that violate a defined minimum air gap (commonly 0.20 to 0.25 mm). Because the courtyard already contains the per-component excess, two touching courtyards still leave the combined clearance both parts requested, so a zero-gap rule is acceptable when the excess values are correct. Overlap errors usually mean parts are too close for the pick-and-place nozzle, the solder stencil aperture, or post-reflow rework with a hot-air pencil. Resolving them by nudging parts apart or reducing the courtyard density level is a routine late-stage placement task.

Q: Why do RF and millimeter-wave layouts need tighter courtyards?

At millimeter-wave frequencies, interconnect parasitics dominate, so designers place components as close together as assembly allows to shorten transmission lines and minimize discontinuity. A bias tee, an LNA die, and its matching network may need centers within 1 to 2 mm, which forces Level C courtyards (0.10 mm excess) or hand-tuned courtyards smaller than the IPC default. The trade-off is manufacturability: tighter courtyards raise placement-accuracy demands on the pick-and-place machine (often a 0.025 mm placement tolerance) and reduce rework access. RF assemblies on alumina or fused-silica also use wire-bonded die where the courtyard must clear the bond-wire loop and the bonding-tool footprint, not just the die body.

/kohrt-yard/

Defined by IPC-7351 as the keep-out boundary surrounding a component footprint, the courtyard reserves the clearance a part needs for placement, automated assembly, and rework. It is drawn as a closed polygon that wraps the maximum land and body outline plus a small courtyard excess, giving EDA tools a single polygon to test during component placement and design rule checking. When two courtyards overlap, the parts sit too close for the pick-and-place nozzle, stencil, or hot-air rework, so the courtyard becomes the practical limit on packing density in dense RF and millimeter-wave boards. Unlike the silkscreen or copper layers, the courtyard carries no physical feature; it exists purely as a documentation and verification artifact.

Category: Electronic Design Automation

Standard: IPC-7351B

Excess (Level B): 0.25 mm

How the Courtyard Bounds a Footprint

The courtyard is the outermost graphic in a properly built land pattern. IPC-7351 builds it by taking the maximum extent of the component, meaning the largest body outline and the maximum land (pad) protrusion as defined by the part tolerances, and then offsetting outward by a fixed courtyard excess. The result is a rectangle or rounded outline that represents the smallest area the component may legally occupy on the board. Because the excess is baked into the polygon, two adjacent courtyards can be placed edge to edge and still preserve the combined clearance both parts requested, which is why most courtyard rules enforce a zero or small minimum air gap rather than a large one.

IPC-7351 ties the courtyard excess to a three-level density system. Level A (Most, maximum protrusion) is the conservative choice for hand assembly and wave soldering, Level B (Nominal) suits most reflow-assembled boards, and Level C (Least) is reserved for high-density, controlled processes. Each level trades manufacturability margin against board area. A typical 0402 chip resistor might use a 0.10 to 0.15 mm excess at Level C, while a large board-to-board connector keeps the full 0.50 mm Level A excess so that mating, tooling, and inspection access stay clear. The courtyard is conventionally drawn on a 0.05 mm placement grid with a thin 0.05 mm line on a dedicated documentation layer.

For RF and millimeter-wave assemblies the courtyard often becomes the binding constraint long before copper clearance does. Designers want an LNA, its bias network, and matching elements within a millimeter or two to keep transmission lines short, so they drop to Level C courtyards or hand-edit them below the IPC default. That choice ripples back into manufacturing: pick-and-place placement tolerance, stencil aperture spacing, and rework-tool access all have to be re-checked against the tighter outline.

Courtyard Excess and Density Levels

Courtyard Outline (per side):
CY_edge = max(body, land) extent + CPL

Courtyard Protrusion Limit (CPL) by density:
Level A (Most) ≈ 0.50 mm | Level B (Nominal) ≈ 0.25 mm | Level C (Least) ≈ 0.10 mm

Inter-component air gap (DRC):
G = d_center − (CY₁/2 + CY₂/2) ≥ 0

Where CY_edge = courtyard offset from part origin, CPL = courtyard excess added on each side, d_center = center-to-center spacing. Example: two 0402 parts at Level C (0.10 mm) with 1.00 mm body and 1.40 mm courtyard width need d_center ≥ 1.40 mm for a zero-gap pass.

Density Level Comparison

Density Level	IPC Name	Courtyard Excess	Assembly Process	Rework Access	Typical Use
Level A	Most (Maximum)	~0.50 mm	Hand / wave solder	Excellent	Prototypes, connectors
Level B	Nominal (Median)	~0.25 mm	Standard reflow	Good	General commercial boards
Level C	Least (Minimum)	~0.10 mm	Controlled reflow	Limited	Dense / portable / RF
Custom RF	Hand-tuned	0.05 to 0.10 mm	Precision place	Poor	mmWave die + matching
Wire-bond die	Bond-loop aware	Loop + tool clearance	Die attach + bond	None after bond	MMIC on alumina

Common Questions

Frequently Asked Questions

What is courtyard excess and how does IPC-7351 set it?

Courtyard excess is the clearance added on each side between the maximum part outline and the courtyard boundary. IPC-7351B sets it by density: Level A (Most) adds about 0.50 mm, Level B (Nominal) about 0.25 mm, and Level C (Least) about 0.10 mm. Chip parts can use 0.10 to 0.15 mm, while connectors and BGAs keep the wider Level A value. The outline is drawn on a 0.05 mm grid with a thin 0.05 mm line on a documentation layer so it never mixes with silkscreen or copper.

How does courtyard violation checking work in a DRC?

EDA tools store a closed courtyard polygon per footprint and flag any two that overlap or break a minimum air gap (often 0.20 to 0.25 mm). Because the excess is already inside the polygon, touching courtyards still leave the requested clearance, so a zero-gap rule is valid when the excess is correct. Overlap errors mean parts are too close for the placement nozzle, the stencil aperture, or hot-air rework, and are fixed by spacing parts or lowering the density level.

Why do RF and millimeter-wave layouts need tighter courtyards?

At millimeter-wave frequencies parasitics dominate, so parts are packed close to shorten lines and cut discontinuity. An LNA, bias tee, and match may need centers within 1 to 2 mm, forcing Level C (0.10 mm) or hand-tuned courtyards. The cost is manufacturability: placement tolerance tightens to about 0.025 mm and rework access shrinks. Wire-bonded MMIC die add another rule, the courtyard must clear the bond-wire loop and bonding-tool footprint, not just the die body.

Related Terms

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