Semiconductor Fabrication

Corner Case

Q: What is the difference between an SS corner and an FF corner?

SS (slow-slow) and FF (fast-fast) describe opposite extremes of the transistor process spread, usually defined at the plus or minus 3-sigma points. At the SS corner the channel is slower: lower transconductance, lower transit frequency fT, and reduced gain, which makes it the worst case for amplifier gain, noise figure, and oscillator start-up margin. At the FF corner devices are faster with higher gain and higher current draw, making it the worst case for stability, power dissipation, and DC bias current. For RF MMICs, designers typically pair these with low and high supply voltage and the temperature extremes, so an SS corner is often run at minimum VDD and plus 85 degrees C while an FF corner is run at maximum VDD and minus 40 degrees C. A design that passes both, plus the SF and FS skew corners, has margin against essentially the entire fabrication population.

Q: How many corner cases do you simulate for an RF MMIC?

A basic process-only sweep uses the five standard SPICE corners: typical (TT), fast-fast (FF), slow-slow (SS), fast-slow (FS), and slow-fast (SF). Adding voltage and temperature turns each into a PVT case. With three voltage points (min, nominal, max) and three temperatures (for example minus 40, plus 25, plus 85 degrees C), the full grid is 5 process corners times 3 voltages times 3 temperatures, which is 45 PVT corners. Many RF flows also add separate corners for passive components such as plus or minus 10 percent on resistors, plus or minus 15 percent on MIM capacitors, and inductor tolerance, which can push the count into the hundreds. Because exhaustive corner simulation grows quickly, teams often supplement it with Monte Carlo statistical analysis to capture mismatch and find the true worst case rather than assuming it sits at a grid vertex.

Q: Why does the worst-case corner depend on which RF specification you are checking?

Different specifications have opposite sensitivities, so no single corner is worst for everything. Small-signal gain and noise figure degrade at SS, low VDD, and high temperature because gm and fT drop. Output power and efficiency are usually worst at the same slow, hot, low-voltage point. Stability and unwanted oscillation, by contrast, are worst at FF, high VDD, and cold temperature where gain and fT peak. DC bias current and self-heating are worst at FF hot. Input and output match shift with both process and temperature because device capacitances change. For this reason an RF MMIC sign-off table lists the controlling corner separately for each parameter rather than picking one universal worst case.

/kor-ner kays/

An extreme combination of process, supply voltage, and temperature (a PVT corner) at which a circuit is simulated and measured to prove it still meets specification across the full fabrication spread. In RF MMIC and RFIC work, a corner case pairs a process corner such as slow-slow or fast-fast with worst-case VDD and the temperature limits, then re-runs the design against vendor SPICE models drawn from the foundry process design kit. The corner that controls gain and noise figure (slow, hot, low voltage) is usually opposite the corner that controls stability and bias current (fast, cold, high voltage), so sign-off tables list a different worst-case corner for each parameter. Designing to the corners rather than the typical case is what separates a part that yields at 30 percent from one that yields above 95 percent.

Category: Semiconductor Fabrication

Process spread: ±3σ (SS to FF)

Typical PVT grid: 5 × 3 × 3 = 45 corners

Process, Voltage, and Temperature Corners in MMIC Design

The phrase comes from the idea of a multi-dimensional design space whose axes are manufacturing and operating variables. The "corners" are the vertices of that space, the simultaneous extremes where parameters reach their limits. In a GaAs pHEMT or GaN MMIC process the dominant axis is the device process corner, which the foundry characterizes from wafer lot statistics and distributes as named SPICE model sets: typical (TT) plus the fast (FF) and slow (SS) extremes of the FET population. Fast means higher transconductance and higher transit frequency f_T; slow means the opposite. The fast-slow (FS) and slow-fast (SF) skew corners familiar from CMOS describe the relative speed of complementary n-channel and p-channel devices, which do not both exist in a single-carrier III-V HEMT process; on those technologies the analogous skew comes from FET-versus-passive variation, so a foundry may instead ship a fast-device / slow-passive corner and its complement. These are anchored at roughly the ±3σ points of the measured population, so a circuit that passes them is robust against nearly every wafer the fab will ship.

Voltage and temperature form the other two axes. A radar transmit module qualified to MIL standards must hold specification from minus 40 to plus 85 degrees C (sometimes plus 125 degrees C for junction-limited parts) and across a supply tolerance of typically ±5 to ±10 percent. Combining the five process corners with three voltage points and three temperatures produces a 45-case PVT grid that is the workhorse of pre-tape-out verification. Passive elements add further corners: thin-film resistors vary ±10 percent, MIM capacitors ±15 percent, and spiral inductors shift with metal thickness, each pulling matching networks and resonant frequencies off nominal.

The critical insight is that the worst case is parameter-specific. Gain, noise figure, and small-signal match degrade at the slow-hot-low-voltage vertex because g_m and f_T collapse there. Stability margin, oscillation risk, and quiescent current are worst at the fast-cold-high-voltage vertex where gain peaks. Because the true minimum of a nonlinear RF metric does not always sit exactly on a grid vertex, modern flows back up deterministic corner runs with Monte Carlo statistical analysis to catch mismatch-driven outliers a coarse grid would miss.

Quantifying Corner Spread and Design Margin

Process corner anchoring (speed metric such as f_T):
X_FF ≈ μ + 3σ and X_SS ≈ μ − 3σ

Worst-case design margin:
Margin = Spec − max[ Result(c) ] over all corners c

PVT corner count:
N_corners = N_process × N_voltage × N_temp

Gain shift with temperature (approx, per device):
ΔG ≈ −0.01 to −0.03 dB/°C × ΔT

Where μ and σ are the lot mean and standard deviation of a process parameter such as f_T. The sign of the offset is parameter-dependent: at the fast corner f_T sits near μ + 3σ while threshold voltage V_th sits near μ − 3σ, since lower V_th yields a faster device. Example: 5 process × 3 voltage × 3 temperature corners = 45 PVT cases; a stage losing 0.02 dB/°C across a 125 °C span drops about 2.5 dB at the hot corner.

Corner Definitions and Their Controlling RF Specifications

Corner	Process / V / T	Device behavior	Worst case for	Typical impact vs. TT
TT (typical)	Nominal / nom / +25 °C	Mean f_T, mean g_m	Reference / yield center	Baseline
SS slow-hot-low	−3σ / min V_DD / +85 °C	Low g_m, low f_T	Gain, NF, P_out, start-up	−2 to −4 dB gain
FF fast-cold-high	+3σ / max V_DD / −40 °C	High g_m, high f_T	Stability, I_DQ, dissipation	+2 to +4 dB gain, +30% I_DQ
FS / SF (skew)	Opposed device speeds	n vs. p skew (CMOS) or FET vs. passive skew (III-V)	Bias balance, match, LO drive	Offset, timing or tuning shift
Passive corners	R ±10%, C ±15%	Shifted RC, resonance	Match, filter f₀, bandwidth	±5 to ±15% on f₀

Common Questions

Frequently Asked Questions

What is the difference between an SS corner and an FF corner?

SS (slow-slow) and FF (fast-fast) are opposite extremes of the transistor spread, set near ±3σ. SS devices have lower g_m and f_T, so SS at low V_DD and high temperature is the worst case for gain, noise figure, and oscillator start-up. FF devices are faster with higher current, so FF at high V_DD and cold temperature is the worst case for stability and bias current. A design passing both, plus the SF/FS skew corners, has margin against the full fabrication population.

How many corner cases do you simulate for an RF MMIC?

A process-only sweep uses five SPICE corners (TT, FF, SS, FS, SF). Adding three voltages and three temperatures gives a 5 × 3 × 3 = 45-case PVT grid. Separate passive corners (R ±10%, MIM C ±15%, inductor tolerance) can push the count into the hundreds, so teams supplement deterministic corners with Monte Carlo analysis to capture mismatch and find the true worst case rather than assuming it sits on a grid vertex.

Why does the worst-case corner depend on which RF specification you are checking?

Specifications have opposite sensitivities. Gain, noise figure, and output power are worst at the slow, hot, low-voltage point where g_m and f_T fall. Stability, quiescent current, and self-heating are worst at the fast, cold, high-voltage point where gain and f_T peak. Match shifts with both process and temperature as device capacitances change. A sign-off table therefore records the controlling corner per parameter instead of one universal worst case.

Related Terms

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