Specific RF Devices

Core Chip

Q: What functions does a phased-array core chip integrate on one die?

A typical core chip integrates a digital phase shifter, a digital step attenuator (for amplitude tapering and gain control), a transmit/receive switch or pair of switches, and a low-power gain stage or driver. Many designs also fold in a serial-to-parallel interface (SPI) and on-chip latches so a single 4-wire bus can address and program the chip. By combining what used to be four to six discrete MMICs into one die, a core chip cuts the per-element parts count, assembly steps, and tile area in an active electronically scanned array. The high-power final amplifier and the low-noise amplifier are usually kept on separate GaN or GaAs dies because their device technologies and thermal needs differ from the control functions on the core chip.

Q: How many bits of phase and amplitude control do core chips provide?

Most production core chips use a 6-bit phase shifter, giving a least significant bit (LSB) of 360/64 = 5.625 degrees, and a 5- or 6-bit attenuator with a 0.5 dB LSB over a 15 to 31.5 dB range. Six bits of phase is the common choice because the resulting RMS quantization error of about 1.6 degrees keeps beam-pointing error and quantization sidelobes acceptable for radar and SATCOM while limiting die area and digital pin count. A 5-bit design (11.25 degree LSB) is sometimes used at lower frequencies or where cost dominates, and 7-bit parts appear in precision instrumentation arrays.

Q: Why are core chips usually GaAs rather than GaN?

Core chips handle small-signal control functions (phase shifting, attenuation, switching) where the figure of merit is low insertion loss, fine resolution, and small die area, not raw power. GaAs pHEMT and FET switch processes offer mature, low-cost, high-yield control MMIC libraries with excellent linearity at the milliwatt to few-hundred-milliwatt levels seen inside a transmit/receive module before the final power amplifier. GaN is reserved for the high-power amplifier stage where its higher breakdown voltage and power density matter. Some highly integrated SiGe BiCMOS core chips push even further by adding the digital control and beamforming logic, which is attractive at millimeter-wave 5G frequencies.

/kor chip/

A multifunction MMIC that folds the control electronics of a single antenna element, the digital phase shifter, the variable attenuator, and the transmit/receive switching, onto one semiconductor die. Sometimes called a multifunction chip (MFC), the core chip is the building block that lets a phased array scale to thousands of elements: by collapsing four to six discrete devices into a single GaAs or SiGe part, it slashes per-element cost, assembly steps, and tile footprint. A typical X-band core chip carries a 6-bit phase shifter (5.625° LSB) and a 5- to 6-bit attenuator (0.5 dB LSB) addressed over an on-chip serial bus, leaving only the high-power final amplifier and low-noise amplifier on separate dies.

Category: Specific RF Devices

Phase resolution: 6-bit (5.625° LSB)

Process: GaAs pHEMT / SiGe

Why Core Chips Made Large Active Arrays Affordable

An active electronically scanned array (AESA) steers its beam by setting a different phase, and often a different amplitude, at every radiating element. In early arrays each element needed a small stack of discrete parts: a phase shifter, an attenuator, one or two switches, and a driver, each in its own package with its own bias lines and its own assembly cost. For an array of 1,000 elements that meant thousands of placements, wire bonds, and tuning steps. The core chip changed the economics by integrating all of the small-signal control onto a single die, so one pick-and-place operation and one serial control bus replace an entire sub-assembly. This is the single biggest reason large digital and analog beamforming arrays moved from niche defense radars into commercial SATCOM ground terminals and 5G millimeter-wave base stations.

A core chip is deliberately a control device, not a power device. It operates on small signals upstream of the high-power amplifier on transmit and downstream of the low-noise amplifier on receive, so its design priorities are low insertion loss, fine phase and amplitude resolution, good linearity, and minimum die area, rather than raw output power. That is why core chips are dominated by mature GaAs pHEMT and FET-switch processes, with SiGe BiCMOS gaining ground at millimeter-wave because it can also absorb the digital beam-steering logic onto the same die. The high-power transmit stage stays on a separate GaN or GaAs die where breakdown voltage and thermal handling, not control granularity, govern the design.

Phase and Amplitude Quantization

Because a core chip sets phase and amplitude in discrete steps, the array suffers quantization error. With an N-bit phase shifter the least significant bit is 360°/2^N, and the worst-case error is half an LSB. The RMS phase error across many randomly distributed settings is the LSB divided by the square root of 12, which is what raises the quantization sidelobe floor and adds a small beam-pointing error. Six bits is the industry sweet spot: it yields an LSB of 5.625° and an RMS error near 1.6°, low enough for most radar and SATCOM beams while keeping the digital interface and die area compact.

Phase shifter LSB (N bits):
LSB = 360° / 2^N  (6-bit → 5.625°)

RMS phase quantization error:
φ_rms = LSB / √12 ≈ 0.289 × LSB

Quantization sidelobe level (approx):
SLL_q ≈ −6.02 × N dBc  (6-bit ≈ −36 dBc)

Attenuator LSB (M bits over range R):
LSB_dB = R / (2^M − 1)  (31.5 dB, 6-bit → 0.5 dB)

Where N = phase bits, M = attenuator bits, R = total attenuation range. A 6-bit phase shifter gives φ_rms ≈ 1.6° and a quantization-limited sidelobe floor near −36 dBc.

Core Chip Versus Discrete and Beamformer Integration

Approach	Functions on die	Process	Typical band	Relative per-element cost	Best fit
Discrete MMICs	1 each (PS, ATT, SW separate)	GaAs	S to Ka	1x (baseline)	Low element counts, legacy
Core chip (MFC)	PS + ATT + T/R switch + driver	GaAs pHEMT	X to Ka	0.4 to 0.6x	Radar and SATCOM AESA tiles
SiGe beamformer IC	Multi-element PS + ATT + logic	SiGe BiCMOS	24 to 47 GHz	0.2 to 0.4x	5G mmWave, low-cost arrays
Full T/R on a chip	Core + LNA + driver PA	GaAs / GaN	X to Ku	0.5 to 0.8x	Compact tiles, lower power

Common Questions

Frequently Asked Questions

What functions does a phased-array core chip integrate on one die?

A core chip combines a digital phase shifter, a digital step attenuator for amplitude tapering and gain trim, transmit/receive switching, and usually a small gain stage plus an on-chip serial (SPI) interface and latches. Folding four to six discrete MMICs into one die cuts per-element parts count, assembly steps, and tile area. The final power amplifier and the LNA normally stay on separate GaN or GaAs dies because their device and thermal needs differ.

How many bits of phase and amplitude control do core chips provide?

Most production core chips use a 6-bit phase shifter (5.625° LSB) and a 5- to 6-bit attenuator with a 0.5 dB LSB over a 15 to 31.5 dB range. Six bits is the common choice because the resulting RMS quantization error near 1.6° keeps beam-pointing error and quantization sidelobes acceptable for radar and SATCOM while limiting die area and pin count. Lower-cost 5-bit (11.25° LSB) and precision 7-bit parts also exist.

Why are core chips usually GaAs rather than GaN?

Core chips handle small-signal control where the priorities are low insertion loss, fine resolution, and small die area, not raw power. Mature GaAs pHEMT and FET-switch libraries deliver excellent linearity at the milliwatt levels seen before the final amplifier. GaN is reserved for the high-power stage where breakdown voltage and power density matter. At millimeter-wave, SiGe BiCMOS core chips also absorb the digital beamforming logic on-die.

Related Terms

← Core Core Loss →