Electronic Design Automation

Copper Pour

/KOP-er por/
Filling otherwise empty regions of a PCB layer with a large connected area of copper, almost always tied to ground, defines a copper pour. In RF and microwave layout the pour acts as a ground plane that provides a low-impedance return path, supplies the reference conductor for controlled-impedance transmission lines, spreads heat away from active devices, and shields adjacent signals. When stitched to lower ground layers with closely spaced vias, the pour suppresses parallel-plate cavity modes and surface waves; left floating or under-stitched, the same fill can resonate and degrade return loss. Pours appear on nearly every layer of a modern RF board and are the primary tool the layout engineer uses to manage the EMI and thermal behavior of the design.
Category: Electronic Design Automation
Typical Copper Weight: 0.5 to 2 oz (17 to 70 μm)
Stitch Via Spacing: λ/10 to λ/20

How Copper Pour Shapes RF Board Performance

A copper pour is generated in the layout tool by selecting a polygon region on a given layer, assigning it to a net (almost always GND), and letting the EDA software flood the area with copper while automatically maintaining a defined clearance from every trace, pad, and via on the same net or other nets. The result is a continuous conductive plane that does far more than fill empty space. On the layer directly beneath an RF trace, the pour is the return-current reference: the high-frequency return travels in the copper directly under the signal, concentrated within roughly three trace-widths of the line. Interrupting that path with a slot, an oversized antipad, or a gap forces the return current to detour, adding loop inductance, raising radiated emissions, and corrupting the line impedance.

On outer layers a top-side pour next to a 50 ohm microstrip line converts the structure into grounded coplanar waveguide. That can be a deliberate, beneficial choice because GCPW concentrates fields and reduces dispersion at millimeter-wave frequencies, but it only works when the pour is densely connected to the buried ground with a via fence. The required via pitch scales with frequency: keeping stitching vias below one-twentieth of a guided wavelength prevents the pour from behaving like a resonant patch antenna. At 28 GHz in a PTFE laminate that means vias roughly every 0.25 to 0.30 mm along the line edges.

Thermally, the pour is the cheapest heat spreader on the board. Connecting a power amplifier or driver IC ground pad to a large pour through an array of thermal vias channels junction heat into the copper, which has a conductivity near 400 W/(m·K), orders of magnitude higher than FR-4. For solderability, pads that tie to a pour normally use thermal relief spokes so the copper does not wick heat away during reflow, while high-current and RF ground connections override that with a solid connection plus extra vias.

Stitching, Clearance, and Resonance

The dominant failure mode of a poorly executed pour is unintended resonance. Two pours on adjacent layers form a parallel-plate cavity; if its dimensions approach a half guided wavelength, the cavity resonates and isolation between channels collapses. Stitching vias short the plates together at intervals small enough to push every cavity resonance above the band of interest. The same vias keep the entire pour at a single ground potential, which is what makes shielding and the return-path benefits real rather than nominal.

Copper Pour Governing Relationships

Maximum stitch-via spacing for cavity suppression:
s ≤ λg / 20  (sensitive RF),  s ≤ λg / 10  (general shielding)
where  λg = c / (f × √εeff)

Parallel-plate cavity resonance (rectangular pour, sides a × b):
fmn = (c / 2√εr) × √( (m/a)2 + (n/b)2 )  ⇒  lowest mode f10 = c / (2 a √εr), a = longest side

Thermal-via path resistance (N vias in parallel):
Rth ≈ (L / (k × Acu)) / N,  Acu = π × (d × tplate)

c = speed of light, εeff = effective permittivity, εr = substrate permittivity, k ≈ 400 W/(m·K) for copper, L = board thickness, d = via diameter, tplate = plating thickness. Example: at 28 GHz with εeff ≈ 2.9, λg ≈ 6.3 mm, so λg/20 ≈ 0.31 mm stitch pitch.

Pour Connection and Stitching Reference

ParameterLow Frequency (< 1 GHz)Microwave (1 to 18 GHz)mmWave (18 to 110 GHz)Design Note
Stitch via pitch2 to 5 mm0.5 to 1.5 mm0.2 to 0.4 mmScale with λg/20
Trace-to-pour clearance3 × W2.5 to 3 × W2 to 2.5 × W (GCPW)Or design as intentional GCPW
Copper weight1 to 2 oz0.5 to 1 oz0.5 ozThin copper aids fine etch tolerance
Pad connectionThermal reliefRelief (signal) / solid (RF GND)Solid + via arrayRelief eases soldering
Floating pour riskLowModerateHigh (patch resonance)Always stitch to GND
Common Questions

Frequently Asked Questions

Should a copper pour under an RF microstrip line be removed or kept?

The microstrip reference is the solid ground plane directly beneath the trace, not a coplanar pour on the same layer. A top-side pour beside a 50 ohm line creates grounded coplanar waveguide, lowering effective impedance and narrowing the required width. If GCPW is intended, stitch the pour to the buried ground every λg/20 (roughly 0.3 mm at 28 GHz, near 0.5 mm at the low end of mmWave); an unstitched floating pour resonates, couples energy, and wrecks return loss. Otherwise keep 2.5 to 3 × the trace width of clearance.

How far apart should stitching vias be in an RF ground pour?

Keep spacing a small fraction of the shortest wavelength: below λg/10 for general shielding and below λg/20 for via fences and sensitive structures. At 28 GHz the guided wavelength in PTFE or FR-4 (εeff ≈ 3 to 4) is about 5 to 6 mm, so λ/20 means vias every 0.25 to 0.30 mm. At 2.4 GHz a few millimeters suffices. Tighter stitching lowers ground impedance and suppresses parallel-plate cavity modes between adjacent pours.

What thermal relief settings should a copper pour use for solderable pads?

A solid pour connection wicks heat during reflow and causes cold joints or tombstoning. Use thermal relief: four 0.25 to 0.5 mm spokes with a 0.25 to 0.4 mm gap at 90 degrees. For RF ground returns and heat-sinking vias, override relief with a solid connection plus extra stitching to minimize inductance, accepting the harder soldering. Internal power and ground planes usually use solid connections because reflow heats the whole board uniformly.

RF PCB & Assembly Design

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From grounded-coplanar mmWave laminates to thermally optimized power-amplifier carriers, our engineering team designs the pour, stitching, and stackup for your integrated assemblies. Talk to us about your next RF layout.

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