Emerging RF Technology

Compute-in-Sensor

Q: How does compute-in-sensor differ from near-sensor and edge computing?

The three approaches differ by where processing physically sits relative to the transduction element. Compute-in-sensor embeds the computation inside the pixel or array, often in the analog domain before the ADC, so the data is reduced at the source. Near-sensor computing places a separate processor in the same package or on the same board, after the ADC but before any long interconnect. Edge computing runs on a gateway or local server reached over a bus or radio link. Each step away from the array adds data-movement energy and latency: an analog in-array multiply costs on the order of femtojoules, an off-chip 12-bit ADC sample costs hundreds of picojoules to nanojoules, and moving a frame over a SerDes or wireless link costs orders of magnitude more. Compute-in-sensor wins when the first processing layer discards most of the raw data, such as detecting motion, beamforming, or running a small convolutional front end.

Q: Why is analog in-array multiply-accumulate so much more efficient than digital?

In an analog crossbar, each sensed value is encoded as a voltage or a charge, and the weights are stored as conductances in a resistive or capacitive element. Ohm's law performs the multiply (current equals conductance times voltage) and Kirchhoff's current law performs the accumulate (currents on a shared column sum automatically). A full vector-matrix multiply happens in one settling time across the whole array, with no per-element clocking, register files, or memory fetches. Reported energy efficiency for analog in-sensor MAC ranges from roughly 1 to 100 tera-operations per second per watt, compared with single-digit TOPS/W for a conventional digital pipeline that must first digitize every sample. The cost is limited precision, typically 4 to 8 effective bits, plus sensitivity to device mismatch, temperature drift, and noise, so analog front ends are paired with digital back ends for the layers that need accuracy.

Q: What sensor types and RF applications use compute-in-sensor today?

The most mature implementations are in CMOS image sensors with in-pixel or column-parallel processing for always-on vision. In the RF and microwave domain, compute-in-sensor maps naturally onto mmWave radar and phased arrays: per-element or per-subarray analog processing performs beamforming, range-FFT pre-conditioning, and clutter rejection before the data rate explodes. FMCW automotive radar at 77 GHz uses in-array dechirp and partial range processing to cut the load on the digital back end. Other targets include event-based vision, biomedical front ends, and acoustic arrays. For RF instrumentation, in-array compute reduces the ADC count and the back-haul bandwidth required from large millimeter-wave aperture arrays, which is the bottleneck as element counts scale into the thousands.

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Embedding the first stages of signal processing directly inside the sensing array, often in the analog domain before any analog-to-digital conversion, defines the compute-in-sensor paradigm. By performing operations such as multiply-accumulate, beamforming, or feature extraction where the signal is captured, the architecture collapses the energy and latency penalty of moving raw data off-chip. This complements edge computing and in-memory computing, but pushes the computation one step further upstream, into the pixel, antenna element, or detector cell itself. In RF and mmWave systems the appeal is direct: a 1,024-element array digitized at gigasample rates can generate hundreds of gigabytes per second of raw samples, and reducing that flood at the source through in-array processing is the only way to keep the digital back end and the data interconnect tractable.

Category: Emerging RF Technology

Analog MAC efficiency: 1 to 100 TOPS/W

Front-end latency: < 1 μs

Moving Computation Into the Detector Array

Conventional sensor chains follow a strict pipeline: transduce the physical signal, amplify and filter it in an analog front end, digitize every sample with an ADC, then ship the digital stream to a processor over a bus or radio link. That pipeline spends most of its energy not on computation but on data movement. A single 12-bit ADC conversion costs on the order of hundreds of picojoules, and moving a frame across a SerDes link or a wireless channel costs orders of magnitude more. When the application only needs a decision (is there motion, which direction is the target, is this a valid waveform), digitizing and transmitting the full raw stream wastes the bulk of the energy budget. Compute-in-sensor inverts the order of operations by doing the first, most data-reducing layer of processing inside the array.

The classic realization is the analog crossbar. Sensed values drive the rows of a resistive or capacitive array, weights are stored as device conductances at each crosspoint, and the physics of the array performs the arithmetic for free. Ohm's law turns each crosspoint into a multiplier, and Kirchhoff's current law sums the column currents into an accumulated result. A complete vector-matrix multiply settles across the whole array in a single analog operation, with no clocked memory fetches. The output is digitized only after this reduction, so the ADC and the downstream link see a far smaller data rate. This is the same primitive that powers in-memory computing, applied at the very front of the signal chain.

The trade-off is precision. Analog computation typically delivers 4 to 8 effective bits and is sensitive to device mismatch, temperature drift, and thermal noise, so in-sensor front ends are paired with conventional digital back ends that handle the layers needing full accuracy. The design problem is partitioning: which layers tolerate analog approximation and live in the array, and which must be digital. For RF arrays this partition usually places beamforming, dechirp, and coarse detection in-sensor, while fine estimation and classification stay digital.

Governing Relations for In-Array Compute

Analog crossbar column output (vector-matrix multiply):
I_j = Σ_i G_ij × V_i (Ohm + Kirchhoff)

Energy per MAC operation:
E_MAC ≈ C × V² → ~1 to 100 fJ (analog) vs ~1 to 10 pJ (digital)

Data-rate reduction factor:
R = (N_elements × f_s × b_raw) / (N_features × f_out × b_out)

Where G_ij = stored conductance (weight), V_i = sensed input, C = effective node capacitance, f_s = sample rate, b = bit depth. Example: a 16 × 16 (256-element) mmWave subarray sampled at 2 GS/s with 12-bit raw resolution, reduced to 8 beam outputs at 1 MS/s × 8 bits, yields R = (256 × 2 GS/s × 12) / (8 × 1 MS/s × 8) ≈ 96,000× less data leaving the array.

Architecture Comparison Across the Processing Continuum

Approach	Compute location	Domain	Typical efficiency	Latency	Best application
Compute-in-sensor	Inside pixel / array element	Analog (pre-ADC)	1 to 100 TOPS/W	< 1 μs	Beamforming, always-on detection
Near-sensor computing	Same package / board	Digital (post-ADC)	1 to 10 TOPS/W	1 to 100 μs	Local feature extraction
Edge computing	Gateway / local node	Digital	0.1 to 5 TOPS/W	0.1 to 10 ms	Aggregation, inference
Cloud / central	Remote data center	Digital	< 0.5 TOPS/W net	10 to 500 ms	Training, heavy analytics

Common Questions

Frequently Asked Questions

How does compute-in-sensor differ from near-sensor and edge computing?

The difference is where processing sits relative to the transducer. Compute-in-sensor embeds computation inside the pixel or array, usually analog and before the ADC, so data is reduced at the source. Near-sensor places a separate processor in the same package after the ADC; edge computing runs on a gateway over a bus or radio link. Each step away adds data-movement energy: an analog in-array multiply costs ~femtojoules, an off-chip ADC sample costs hundreds of pJ to nJ, and moving a frame over SerDes or wireless costs far more.

Why is analog in-array multiply-accumulate so much more efficient than digital?

In an analog crossbar, sensed values are voltages and weights are stored conductances. Ohm's law does the multiply (I = G × V) and Kirchhoff's current law does the accumulate, so a full vector-matrix multiply completes in one settling time with no per-element clocking or memory fetch. Reported efficiency runs roughly 1 to 100 TOPS/W versus single-digit TOPS/W for a digital pipeline that must digitize every sample first. The cost is 4 to 8 effective bits plus mismatch, drift, and noise, so analog front ends pair with digital back ends.

What sensor types and RF applications use compute-in-sensor today?

The most mature designs are CMOS image sensors with in-pixel or column-parallel processing for always-on vision. In RF and microwave systems, compute-in-sensor maps onto mmWave radar and phased arrays for per-element beamforming, range-FFT pre-conditioning, and clutter rejection before the data rate explodes. FMCW automotive radar at 77 GHz uses in-array dechirp to offload the digital back end. It also reduces the ADC count and back-haul bandwidth from large millimeter-wave aperture arrays scaling into the thousands of elements.

Related Terms

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