How does COB reduce RF parasitics compared to packaged ICs?

A standard QFN package adds approximately 0.5 to 2 nH of lead inductance, 0.1 to 0.5 pF of pad-to-ground capacitance, and 0.05 to 0.2 dB of interconnect loss per signal pin. At 28 GHz, 1 nH of inductance represents 176 ohms of reactance, severely mismatching a 50-ohm system and requiring additional matching network area that itself introduces loss. COB eliminates the package entirely: wire bonds from die pads to substrate pads are typically 0.3 to 1 mm long with 0.3 to 0.7 nH inductance (versus 1 to 5 mm bond wire plus lead frame in a package). Flip-chip bumps have even lower parasitics: 10 to 50 pH inductance and 10 to 30 fF capacitance per bump, essentially negligible up to 100 GHz. The shorter signal path also reduces coupling to adjacent signals and ground bounce. The total parasitic reduction from COB versus QFN packaging is typically 50 to 80% in inductance and 60 to 90% in capacitance, directly translating to improved gain, noise figure, and bandwidth.

What are the thermal advantages of COB?

In a packaged IC, heat must flow from the die through the die attach adhesive (thermal resistance 1 to 10 K/W), through the lead frame or package substrate, through the solder joints, and finally to the PCB. Total junction-to-board thermal resistance for a QFN package is typically 15 to 40 K/W. In COB, the die is attached directly to the substrate using high-conductivity die attach materials (silver-filled epoxy at 1 to 3 W/mK, eutectic gold-tin solder at 57 W/mK, or sintered silver at 200+ W/mK). The direct attachment reduces junction-to-board thermal resistance to 3 to 15 K/W, a 50 to 75% improvement. For high-power RF amplifiers dissipating 1 to 10 W, this translates to 20 to 50 degrees C lower junction temperature, directly improving reliability (junction temperature is the primary accelerating factor for semiconductor failure). COB on aluminum nitride (AlN) ceramic substrates achieves the best thermal performance, with substrate thermal conductivity of 170 to 200 W/mK versus 0.3 to 0.5 W/mK for standard FR-4 PCB.

When should COB be used instead of packaged components?

COB is justified when package parasitics limit performance at the target frequency, when thermal dissipation requirements exceed package capability, when module size must be minimized, or when the application volume is too low to justify custom package development. Common RF applications include military and aerospace modules where bare GaAs or GaN MMIC die are assembled on alumina or AlN substrates in hermetically sealed housings, satellite communication transponder modules, phased array T/R modules where hundreds of identical die are assembled on a single substrate, and prototype or low-volume mmWave products where the die is available from foundry but custom packaging would cost 100K to 500K dollars in NRE. COB is not recommended for high-volume consumer products (where packaged ICs are cheaper due to automated pick-and-place versus manual die attach), applications below 6 GHz (where package parasitics are manageable), or when known good die testing is not available (COB commits bare die before board-level testing, with no rework option for bad die).

Manufacturing

COB

/see-oh-bee/

Chip-on-Board (COB) mounts bare semiconductor die directly onto PCB or ceramic substrates via wire bonding or flip-chip. Eliminates package parasitics (50 to 80% reduction in inductance, 60 to 90% in capacitance), extends usable frequency 30 to 50% vs same die in QFN. Direct die attach reduces thermal resistance 50 to 75% (3 to 15 K/W vs 15 to 40 K/W packaged). Essential for mmWave MMIC modules, phased array T/R modules, and military/aerospace RF assemblies above 10 GHz.

Category: Manufacturing

Parasitic reduction: 50 to 80%

Thermal R_th: 3 to 15 K/W

Understanding COB Assembly

As operating frequencies push into the mmWave range (above 24 GHz), the IC package increasingly becomes the performance bottleneck rather than the silicon or GaAs die itself. A state-of-the-art GaN PA die may provide 20 dB gain at 28 GHz, but packaging it in a standard QFN adds 1 to 2 nH of lead inductance and 0.3 pF of parasitic capacitance per RF pin, reducing gain by 3 to 5 dB and degrading return loss from -20 dB to -8 dB. COB bypasses this problem entirely: the bare die is epoxied directly to the substrate and connected to the circuit traces using short wire bonds (0.3 to 1 mm) or flip-chip solder bumps (50 to 100 μm), preserving the die-level performance through the assembly step.

The trade-off is manufacturing complexity. Packaged ICs are tested before assembly (known good die), can be placed by standard pick-and-place machines at rates of 10,000+ per hour, and are protected by the package from mechanical damage and moisture. COB requires bare die procurement (not all foundries sell bare die), specialized die attach equipment (eutectic or epoxy die bonder with ±5 μm accuracy), wire bonding machines (25 μm gold or aluminum wire, ball-wedge or wedge-wedge), and encapsulation or hermetic sealing. These processes are slower and more expensive per unit than packaged IC assembly, limiting COB to military/aerospace, satellite, low-volume mmWave, and phased array applications where performance justifies the cost premium.

COB vs Packaged IC Parameters

Wire Bond Inductance:
L ≈ 1 nH/mm × length

Flip-Chip Bump Parasitic:
L ≈ 10 to 50 pH, C ≈ 10 to 30 fF per bump

Thermal Resistance (direct attach):
R_th = t/(k × A) (K/W)

Where t = die attach thickness (10 to 50 μm), k = thermal conductivity (1 to 200 W/mK), A = die area. AuSn solder (k=57 W/mK), 25 μm thick, 2×2 mm die: R_th = 0.11 K/W at the attach alone.

COB Assembly Comparison

Parameter	QFN Package	COB Wire Bond	COB Flip-Chip
Lead inductance	0.5 to 2 nH	0.3 to 0.7 nH	10 to 50 pH
Pad capacitance	0.1 to 0.5 pF	0.05 to 0.2 pF	10 to 30 fF
Thermal R_th	15 to 40 K/W	5 to 15 K/W	3 to 10 K/W
Max frequency	20 to 40 GHz	40 to 80 GHz	100+ GHz
Assembly cost	Low (automated)	Medium (manual)	High (precision)

Common Questions

Frequently Asked Questions

How does COB reduce RF parasitics?

Eliminates package lead frame (0.5 to 2 nH, 0.1 to 0.5 pF per pin). Wire bonds: 0.3 to 0.7 nH (0.3 to 1 mm length). Flip-chip: 10 to 50 pH, 10 to 30 fF per bump (negligible to 100 GHz). At 28 GHz, 1 nH = 176 Ω reactance, severe mismatch. COB improves gain 3 to 5 dB and extends bandwidth 30 to 50% vs same die in QFN.

What are the thermal advantages?

Direct die attach eliminates package layers. R_th drops from 15 to 40 K/W (QFN) to 3 to 15 K/W (COB). For 5 W PA: 20 to 50°C lower junction temperature. Best: AuSn solder on AlN ceramic (k = 170 W/mK vs FR-4 at 0.3 W/mK). Sintered silver: 200+ W/mK conductivity.

When should COB be used?

Above 10 GHz where package parasitics limit performance. High thermal loads exceeding package capability. Military/aerospace modules on alumina/AlN substrates. Phased array T/R modules (hundreds of die per substrate). Not recommended for: consumer high-volume (<6 GHz), when bare die not available, or when rework is needed.

Related Terms

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COB