A CMOS PA is a power amplifier built in a standard silicon CMOS process rather than in a compound semiconductor such as GaAs or GaN. Its appeal is integration: the PA can sit on the same die as the low-noise amplifier, mixer, phase shifter, and even digital control, which is essential for the large phased-array beamformer chips used in millimeter-wave 5G. The challenge is that CMOS transistors have low breakdown voltage and the silicon substrate is lossy, so a CMOS PA delivers less power per device and lower efficiency than a III-V PA. Designers compensate with circuit techniques that combine many small cells and protect the devices from voltage stress.

Why is it hard to build a high-power CMOS PA?

Output power scales with the square of the voltage swing the transistor can sustain, and CMOS devices have breakdown voltages of only one to two volts, far below the tens of volts a GaN device tolerates. The lossy silicon substrate also wastes energy in the matching and combining networks, and the low knee voltage relative to breakdown limits the usable swing. The practical result is that a single CMOS cell at millimeter-wave frequencies produces only around 10 to 15 dBm. Reaching useful transmit power requires combining many cells, which adds combiner loss, and managing the heat and reliability of devices operated near their voltage limits.

How do CMOS PAs reach useful millimeter-wave power?

Several techniques are used together. Stacked-FET cells put two to four transistors in series so the output voltage swing, and thus the power, is shared across devices that each stay within breakdown. Transformer-based and distributed-active-transformer combining sum the outputs of many parallel cells on chip with relatively low loss. Doherty and outphasing architectures improve efficiency at the power back-off where high-order modulation operates. Above all, millimeter-wave 5G uses large phased arrays, so the total radiated power is built up in the air by combining many antenna elements, each driven by a modest CMOS PA, rather than demanding high power from any single amplifier.

mmWave & 5G

CMOS PA

/see-moss pee-ay/ (CMOS Power Amplifier)

A CMOS PA is a radio-frequency power amplifier fabricated in a standard CMOS process, most often for millimeter-wave 5G NR FR2 phased arrays. It overcomes the low breakdown voltage and lossy silicon substrate of CMOS with stacked-FET cells, transformer-based on-chip power combining, and linearization, reaching per-element saturated output around 15 to 20 dBm at power-added efficiency of roughly 20 to 35 percent. Its decisive advantage is integration: the PA shares a die with the rest of the transceiver, enabling compact, low-cost beamformer ICs.

Category: mmWave & 5G

Per-element P_sat: ~ 15 to 20 dBm

PAE: ~ 20 to 35%

Understanding the CMOS PA

The power amplifier is the last active stage in a transmitter and historically the hardest to integrate, which is why it was long built in compound semiconductors such as GaAs and GaN that handle high voltage and dissipate heat well. The pull toward CMOS comes from the economics and density of silicon. A millimeter-wave 5G base station or handset array needs dozens to hundreds of transmit elements, each with a phase shifter, a variable-gain amplifier, and a PA. Putting all of that, plus digital control, on one silicon die in a beamformer IC is only practical if the PA can be built in the same CMOS process. The CMOS PA is the component that makes that integration possible.

The physics fights back. A CMOS transistor in an advanced node may break down above a volt or two, while output power grows with the square of the achievable voltage swing. A lossy silicon substrate, unlike the semi-insulating substrate of GaAs, bleeds energy out of inductors, transmission lines, and the combining network. The knee voltage, the point where the device leaves its useful saturation region, eats further into the swing. Together these mean a single CMOS device at 28 or 39 GHz manages only around 10 to 15 dBm, an order of magnitude below a comparable GaN cell.

Stacking, Combining, and the Array Advantage

CMOS PA design is largely the art of getting around the voltage limit. Stacked-FET cells place two, three, or four transistors in series so that the total output swing is divided among devices that each stay safely below breakdown, multiplying the deliverable power. On-chip transformers and distributed active transformers then combine the outputs of many parallel cells with manageable loss, while also performing impedance transformation to the antenna. For the amplitude-varying, high-peak-to-average waveforms of 5G, Doherty and outphasing architectures keep efficiency from collapsing at back-off. The deepest advantage, though, is the phased array itself: because radiated power combines in space, an array of N elements each emitting modest power produces an effective isotropic radiated power that scales strongly with N, so a fleet of small CMOS PAs delivers the link budget that no single silicon amplifier could.

CMOS PA Design Equations

Class-A output power limit:
P_out ≈ (V_max − V_knee)² / (8 R_L)

Stacked-FET swing (n devices):
V_swing ≈ n × (V_max − V_knee)

Power-added efficiency:
PAE = (P_out − P_in) / P_DC

Where V_max = peak safe drain voltage, V_knee = knee voltage, R_L = load resistance, n = number of stacked devices, P_in, P_out = RF powers, P_DC = DC power. Example: a 4-stack roughly quadruples swing, raising P_out by about 6 dB over a single device.

PA Technology Comparison

Technology	Breakdown	Per-cell power (mmWave)	Efficiency	Integration	Best use
CMOS / SOI	~ 1 to 2 V	~ 10 to 15 dBm	20 to 35%	Excellent (full SoC)	5G beamformer arrays
SiGe BiCMOS	~ 2 to 4 V	~ 13 to 18 dBm	25 to 40%	Very good	mmWave arrays, radar
GaAs	~ 10 to 15 V	~ 20 to 27 dBm	30 to 45%	PA-only die	Handset and infra PAs
GaN	> 40 V	~ 30+ dBm	40 to 60%	PA-only die	High-power infra, radar

Common Questions

Frequently Asked Questions

What is a CMOS PA?

It is a power amplifier built in a standard silicon CMOS process instead of GaAs or GaN. Its value is integration: the PA shares a die with the LNA, mixer, phase shifter, and digital control, which is essential for the large millimeter-wave 5G beamformer chips. The trade-off is lower power and efficiency per device than a III-V PA.

Why is a high-power CMOS PA hard?

Output power scales with the square of the safe voltage swing, but CMOS breakdown is only one to two volts versus tens of volts for GaN. The lossy silicon substrate wastes power in matching and combining, and the knee voltage cuts usable swing, so a single cell yields only ~10 to 15 dBm at mmWave.

How do CMOS PAs reach useful power?

Stacked-FET cells put devices in series to share the swing within breakdown; transformer and distributed-active-transformer combining sum many parallel cells on chip; Doherty and outphasing raise back-off efficiency. Above all, large phased arrays combine many modest CMOS PAs in the air to build the link budget.

Related Terms

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