How does CML differ from ECL and CMOS logic?

All three are logic families but they trade speed for power differently. Standard CMOS logic is single-ended and rail-to-rail; it draws almost no static current but its large swing and switching transients limit clean operation at very high frequency. ECL (emitter coupled logic) is the bipolar ancestor of CML, also current-steering and differential, but it uses emitter followers and larger swings referenced to a negative supply. CML strips the design down to a differential pair with resistor loads and a small swing, optimized for the highest speed and easy 50 ohm termination, at the cost of constant static power. In short, CMOS is lowest power, ECL is legacy high speed, and CML is the modern high-speed serial-link choice.

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CML

Q: What is current mode logic (CML)?

Current mode logic is a high-speed digital logic style built around a differential pair and a constant tail current source. The pair steers that fixed current into one of two load resistors depending on the input state, so one output drops while the other stays high, producing a differential voltage swing of roughly 250 to 400 mV. Because the supply current is constant whether the gate is switching or not, CML generates very little supply noise, and the differential signaling rejects common-mode interference. These properties let CML run at data rates from a few gigabits per second to well over 50 Gb/s, which is why it dominates serial link transceivers.

Q: Why is CML terminated in 50 ohms?

At the data rates CML targets, the interconnect between stages or between chips behaves as a transmission line, so the line must be terminated in its characteristic impedance to avoid reflections that would close the eye. CML load resistors are commonly set to 50 ohms (or 100 ohms differential) so the outputs both define the logic swing and match the line. On-chip the termination may be 50 ohms to the positive supply, and chip-to-chip links add receiver-side termination. Matching the impedance keeps rise times clean and the data eye open at multi-gigabit rates.

/see-em-el/ (Current Mode Logic)

CML, current mode logic, is a high-speed differential logic family in which a constant tail current is steered by a differential pair into one of two resistive loads, generating a small swing of roughly 250 to 400 mV. The constant current draw produces low switching noise, and the differential structure rejects common-mode disturbance, so CML operates well into the tens of gigahertz. Its resistor loads double as 50 ohm terminations, making it the default logic style for SerDes transceivers, clock and frequency dividers, and high-speed multiplexers.

Category: Active Components

Swing: ~ 250 to 400 mV

Termination: 50 Ω / 100 Ω diff

Understanding CML

Current mode logic exists because ordinary rail-to-rail logic runs out of speed. A conventional CMOS gate charges and discharges its output between the supply rails on every transition, which dumps large current spikes into the supply and forces the driver to slew a big voltage swing through the load capacitance. At multi-gigahertz clock rates that swing cannot settle cleanly. CML takes a different path: it never moves much voltage and it never changes how much current it draws. A constant tail current source sets the bias, and a differential pair tips that current toward one side or the other based on the input. The side that conducts pulls its load resistor low; the side that does not stays near the supply. The result is a small, fast, differential output.

That small swing is the key to speed. With only a few hundred millivolts to move and a resistive (rather than purely capacitive) load setting the time constant, the outputs transition in picoseconds. Differential operation doubles the effective signal and cancels common-mode noise and supply bounce, while the constant supply current means the gate injects almost no switching transient back into the power distribution network, a property that matters enormously in mixed-signal chips where a sensitive analog block sits next to fast digital logic.

Topology, Speed, and Power

A basic CML cell is a differential pair with two load resistors and a current source; logic functions are built by stacking or replacing the input pair, so a CML latch, multiplexer, or XOR is a compact extension of the same core. Because each output sits at a defined impedance, CML interfaces naturally with 50 ohm transmission lines and is the standard for chip-to-chip serial links. The cost is static power: a CML gate burns its tail current continuously, swing times current, regardless of activity, so a complex CML clock tree can dominate a transceiver's power budget. Designers therefore reserve CML for the fastest blocks (the serializer output, the high-speed divider, the clock distribution) and hand the slower logic back to CMOS, often through a CML-to-CMOS level converter.

CML Design Equations

Output voltage swing (single-ended):
ΔV = I_tail × R_L

Static power per gate:
P = I_tail × V_DD

Output time constant:
τ = R_L × C_L (sets rise/fall time)

Where I_tail = tail current, R_L = load resistor, V_DD = supply, C_L = load capacitance. Example: I_tail = 8 mA into R_L = 50 Ω gives a 400 mV single-ended (800 mV differential) swing.

Logic Family Comparison

Family	Signaling	Typical swing	Static power	Top speed	Best use
CML	Differential	250 to 400 mV	High (constant)	> 50 Gb/s	SerDes, dividers, MUX
ECL	Differential	~ 800 mV	High	~ 10 GHz	Legacy high speed
LVDS	Differential	~ 350 mV	Moderate	~ a few Gb/s	Board-level links
CMOS	Single-ended	Rail-to-rail	Near zero static	Lower	General logic

Common Questions

Frequently Asked Questions

What is current mode logic (CML)?

It is high-speed logic built on a differential pair and a constant tail current source. The pair steers the fixed current into one of two load resistors, giving a 250 to 400 mV differential swing. Constant supply current means low switching noise, and differential signaling rejects common-mode interference, so CML runs from a few Gb/s to well over 50 Gb/s in serial links.

How does CML differ from ECL and CMOS?

CMOS is single-ended, rail-to-rail, and lowest static power but slower. ECL is the bipolar current-steering ancestor with larger swings on a negative supply. CML reduces the design to a differential pair with resistor loads and a small swing, optimized for top speed and 50 ohm termination, at the cost of constant static power.

Why is CML terminated in 50 ohms?

At multi-gigabit rates the interconnect is a transmission line and must be terminated to avoid reflections that close the eye. CML load resistors are set to 50 ohms (100 ohms differential) so they both define the logic swing and match the line, keeping rise times clean and the data eye open.

Related Terms

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