PLL Frequency Synthesizer

Signal Chain Walkthrough

A Phase-Locked Loop (PLL) frequency synthesizer generates a stable, programmable output frequency by locking a voltage-controlled oscillator (VCO) to a crystal reference. The PLL is the fundamental frequency generation architecture in virtually every RF system.

Reference Oscillator

A crystal oscillator (TCXO or OCXO) provides an ultra-stable reference frequency (typically 10 or 100 MHz). All output frequency accuracy and stability traces back to this reference.

Phase/Frequency Detector + Charge Pump

The PFD compares the phase of the divided reference (f_ref/R) with the divided VCO output (f_out/N). The charge pump converts the phase error into a current that drives the loop filter.

Loop Filter

A low-pass filter converts the charge pump output to a smooth DC voltage (V_tune) that controls the VCO. The filter bandwidth determines the PLL's lock time, phase noise profile, and spurious rejection.

VCO

The voltage-controlled oscillator generates the output frequency. Inside the PLL loop bandwidth, the VCO phase noise is suppressed and replaced by the reference noise multiplied by 20·log(N). Outside the loop bandwidth, the VCO's free-running phase noise dominates.

Feedback Divider (/N)

Divides the VCO output by N to produce f_out/N for comparison with f_ref/R. Integer-N PLLs quantize frequency steps to f_ref/R. Fractional-N PLLs use sigma-delta modulation to achieve much finer frequency resolution.